Designing robust performance models for modern complex digital circuits in the face of rapidly accelerating process variations is a critical yet demanding task. This paper introduces an efficient statistical performance modeling approach for VLSI digital circuits that incurs minimal computational expense. The fundamental concept involves capitalizing on knowledge gained from circuit modeling in one technology node to streamline the modeling process in another. This is achieved by merging previously established statistical models of process technology with a limited set of simulation data from a subsequent process technology through transfer learning. Comprehensive experiments conducted across diverse technology nodes demonstrate that the proposed framework is robust, precise, efficient in data usage, and computationally superior to other cutting-edge performance modeling techniques.
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