The design of adder, subtractor, and derivative circuits without the use of op-amp in CNFET Technology

Abstract

The complexity of digital circuits is constantly rising. Analog computing can be an excellent alternative to overcome the complexity issue. Operational Amplifiers play a serious role in many analog circuit designs. This paper presents a new implementation approach to an analog subtractor. This design enjoys high speed and low power dissipation using Carbon Nanotube FETs (CNTFETs). We have also achieved a significant improvement in terms of the number of transistors and chip area. The proposed design considerably decreases power consumption and optimizes the chip area. The same performance can be achieved when designing a high-quality Differentiator. It is to remark that there is no need to use a huge number of resistors and capacitors. In this design, no additional voltage or current sources have been used. HSPICE and the Stanford 32 nm CNTFET model are used to simulate the proposed circuit. The comparisons with State-of-the-art prove the performance of this design.