An 8.2 fJ/conversion-step 9-bit 135 MS/s SAR ADC with redundant methods for acceleration

Abstract

A 9-bit 135 MS/s SAR ADC utilizes a 1.5-bit acceleration method and a binary-scaled recombination weighting method in this paper. These two redundant methods are proposed to alleviate the settling requirement of the DAC circuit and to improve the operation speed of SAR ADC. Meanwhile, no extra capacitors or complex digital circuits are required in this ADC. The prototype ADC is fabricated in 65 nm CMOS technology with an active area of 0.027 mm2. Without any offset or capacitor mismatch calibration, the ADC achieves 8.7-ENOB at 2.4 MHz input and 8.4-ENOB at the Nyquist frequency, respectively. The measured SFDR maintains above 65 dB up to 250 MHz input and the measured ERBW reaches 250 MHz. The power consumption of the ADC core from 1.2 V supply is 0.46 mW and the FoM is 8.2 fJ/conversion-step at a 2.4 MHz input.