Complementary Transistors Research Articles

Strain analysis comparison in complementary and nanosheet field-effect transistor devices: Nanobeam vs Bessel electron diffraction

Strain analysis comparison in complementary and nanosheet field-effect transistor devices: Nanobeam vs Bessel electron diffraction

Large-Scale Vertically Interconnected Complementary Field-Effect Transistors Based on Thermal Evaporation.

With the rapid development of integrated circuits, there is an increasing need to boost transistor density. In addition to shrinking the device size to the atomic scale, vertically stacked interlayer interconnection technology is also an effective solution. However, realizing large-scale vertically interconnected complementary field-effect transistors (CFETs) has never been easy. Currently-used semiconductor channel synthesis and doping technologies often suffer from complex fabrication processes, poor vertical integration, low device yield, and inability to large-scale production. Here, a method to prepare large-scale vertically interconnected CFETs based on a thermal evaporation process is reported. Thermally-evaporated etching-free Te and Bi2S3 serve as p-type and n-type semiconductor channels and exhibit FET on-off ratios of 103 and 105, respectively. The vertically interconnected CFET inverter exhibits a clear switching behavior with a voltage gain of 17 at a 4 V supply voltage and a device yield of 100%. Based on the ability of thermal evaporation to prepare large-scale uniform semiconductor channels on arbitrary surfaces, repeated upward manufacturing can realize multi-level interlayer interconnection integrated circuits.

Design and exploration of vertically stacked complementary tunneling field-effect transistors

The purpose of this letter is to study the design and explore vertically stacked complementary tunneling field-effect transistors (CTFETs) using CFET technology for emerging technology nodes. As a prior work, the CTFET’s device-level simulations are implemented and deliberated in strict compliance with the experimental settings. This work comprises the study of physical and DC analyses by scaling the p- to n-CTFET separation (D pn ), being a significant factor in CFET/CTFET design for its process difficulty. By utilizing the 50% benefit in footprint, the work is further extended to CTFET static random access memory implementation and characterization with hold/read noise margin analysis.

Nanosheet-based complementary transistors with a 48 nm pitch

Nanosheet-based complementary transistors with a 48 nm pitch

Complementary magnon transistors by comb-shaped gating currents

Complementary magnon transistors by comb-shaped gating currents

Progress in the suppression of short-channel effects: Materials and structure

With the rapid development of integrated circuit (IC) technology, the size of devices has been continuously shrinking. While this trend has led to increased integration density, improved device reliability, and reduced costs, it has also resulted in performance degradation of metal-oxide-semiconductor field-effect transistors (MOSFETs) due to the short channel effect (SCE). This paper provides a comprehensive review of the most recent techniques that can mitigate the short channel effect in MOSFETs, with a focus on semiconductor materials and device structures. These techniques include decades-long advancements in doping and high- dielectric materials, as well as emerging structures such as Fin field-effect transistors (FinFETs), Gate-all-around field-effect transistors (GAAFETs), Forksheet field-effect transistors, and complementary field-effect transistors (CFETs). This paper can greatly assist researchers in establishing a theoretical foundation, identifying research problems and voids, and identifying hot spots and trends in short channel effect research through a comprehensive analysis of the existing research literature.

Reliability forecasting and Accelerated Lifetime Testing in advanced CMOS technologies

This study harnesses a machine learning approach to precisely forecast the reliability of 22 nm Bulk Complementary Metal Oxide Transistor (CMOS) and 22 nm Metal Gate High-k (MGK) technologies, particularly at room temperature. Extending its capabilities, it also delves into the realm of varying temperature conditions and the rigors of Accelerated Lifetime Testing (ALT), employing advanced statistical models. This initiative empowers engineers and designers with the knowledge needed to make well-informed decisions concerning the performance and longevity of these advanced semiconductor technologies. Through thorough data analysis and rigorous training, our machine learning framework delivers highly accurate and efficient reliability predictions. Consequently, it enhances the overall quality and durability of 22 nm Bulk CMOS and 22 nm MGK devices. This research stands as a substantial contribution to the semiconductor industry, offering a reliable and efficient solution for reliability prediction, thus ensuring the optimal utilization of these cutting-edge technologies in practical applications.

DC and AC characteristics of Si/SiGe based vertically stacked complementary-tunneling FETs

In this paper, electrical characteristics of a complementary tunneling field effect transistor (CTFET) is studied computationally for the first time. The design of CTFET is carried with 3D vertically stacked channels (multiple) of n-TFET on top of the p-TFET with gate-all-around (GAA) nanosheet SiGe options. The CTFET technology (using CFETs) is examined for emerging technology nodes as a potential alternative to conventional TFETs. Here, the device level design of CTFET is strictly monitored with DC characteristic behavior under the influence of process variability conditions (traps and temperature). The performance analysis is extended to analyze the scalability of CTFET under critical dimensions (n- to p-TFET separation, nanosheet pitch, and so on), and find that it is highly scalable. The circuit analysis of CTFET-inverter show high-noise margin (NM) and voltage gains compared to the conventional strained-Si GAA-TFETs at the supply range (V D D) from 0.7 ≥ V D D ≥ 0.2 V. In addition, the CTFET-inverter circuit performance is analyzed with miller capacitance, power delay product, and intrinsic delay, respectively. Improved circuit performance, followed by 12.5% and 21.5% improvements in low and high NMs (NML and NMH) are seen in CTFETs compared to conventional TFETs.

Designing high-speed and energy-efficient dynamic comparators using complementary carbon nanotube field-effect transistors

Designing high-speed and energy-efficient dynamic comparators using complementary carbon nanotube field-effect transistors

Complementary Two-Dimensional Vertical Transistors through Lamination with a van der Waals Metal

Complementary Two-Dimensional Vertical Transistors through Lamination with a van der Waals Metal

A Buried Thermal Rail (BTR) Technology to Improve Electrothermal Characteristics of Complementary Field-Effect Transistor (CFET).

The complementary field-effect transistor (CFET) with N-type FET (NFET) stacked on P-type FET (PFET) is a promising device structure based on gate-all-around FET (GAAFET). Because of the high-density stacked structure, the self-heating effect (SHE) becomes more and more severe. Buried thermal rail (BTR) technology on top of the buried power rail (BPR) process is proposed to improve heat dissipation. Through a systematical 3D Technology Computer Aided Design (TCAD) simulation, compared to traditional CFET and CFET with BPR only, the thermal resistance (Rth) of CFET can be significantly reduced with BTR technology, while the drive capability is also improved. Furthermore, based on the proposed BTR technology, different power delivery structures of top-VDD-top-VSS (TDTS), bottom-VDD-bottom-VSS (BDBS), and bottom-VDD-top-VSS (BDTS) were investigated in terms of electrothermal and parasitic characteristics. The Rth of the BTR-BDTS structure is decreased by 5% for NFET and 9% for PFET, and the Ion is increased by 2% for NFET and 7% for PFET.

Circuit Design Modernization of Operational Amplifiers for Increasing Slew Rate of Output Voltage

To meet the existing needs of the domestic market of radio electronic equipment in high-speed wideband operational amplifiers, it was previously proposed to use the MH2XA031 master slice array containing complementary bipolar transistors, together with the developed circuits of the OAmp9 high-speed operational amplifier and the OAmp10 precision operational amplifier with unified cascades and the ability to program parameters such as current consumption, maximum output current, bandwidth, slew rate. The article discusses the increase in the performance of these operational amplifiers by reducing the parasitic collector capacitance of transistors by applying a reverse bias voltage to OAmp9 and using correction circuits in OAmp10, which made it possible to increase the output voltage slew rate by 29 % in the first case and 3.1 times in the second. The electrical circuits and the results of circuit simulation of the upgraded amplifiers, called OAmp9M, OAmp10M, are presented, which are respectively characterized by a zero offset voltage of 0.35 and 0.03 mV, a voltage gain of 2.7 · 103 and 3 · 105, the gain bandwidth product 161 and 68 MHz, output voltage slew rate 708 and 64.5 V/µs.

CMOS-Compatible Titanium-Based Micro Supercapacitor With Outstanding Capacitance and Frequency Performances

Micro supercapacitors (MSCs) with high capacitance density offer enormous potential for on-chip energy storage and power supply filtering. However, the capacitance decay under an AC condition and incompatibility with Complementary Metal Oxide Semiconductor Transistor (CMOS) processes greatly restrict their application as filtering capacitors in integrated circuits. This work presents a wafer-level MSC with outstanding capacitance and frequency performances, contributed by the hybrid TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Ti electrode structure and a novel CMOS-compatible fabrication methodology. The highly conductive Ti framework with optimal porous structure provides a fast transfer channel for electrons/ions, while a 6 nm-thick TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , in situ oxidized-grown on the Ti framework, offers exceptional pseudocapacitance. Meanwhile, a 3D electrode architecture is fabricated through a proposed High-Aspect-Ratio Porous Electrode Lift-off (HPEL) process, benefiting capacitance and rate performance. Hence, the MSC shows a capacitance density of 10.12 mF/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at a high scan rate of 1 V/s with a characteristic frequency of 550 Hz, which is superior to the reported on-chip MSCs. Furthermore, such proposed design and fabrication strategies are simple, low-cost, and CMOS-compatible, promising for mass production.

Potential of Transition Metal Dichalcogenide Transistors for Flexible Electronics Applications

AbstractSemiconducting transition metal dichalcogenides (TMDC) are 2D materials, combining good charge carrier mobility, ultimate dimension down‐scalability, and low‐temperature integration. These properties make TMDCs interesting for flexible electronics, where the thermal fabrication budget is strongly substrate limited. In this perspective, an overview of the state of TMDC research is provided by evaluating two scenarios, both with their own merit depending on the target application. First, high‐quality chemically grown 2D TMDCs are promising for nanoscale high‐performance and high‐frequency devices with excellent gate control and high current on/off ratios. Second, TMDC thin films can also be solution deposited from chemically exfoliated flakes allowing for moderate performance, but providing a path toward low‐cost production. A strong advantage of TMDCs is the possibility to realize p‐type and n‐type channels for complementary transistors having similar performance figures‐of‐merit. This aspect, as well as common transistor performance metrics are also compared with other flexible channel materials providing an overview of the state of the art of thin‐film transistors in the field of flexible electronics.

Performance comparison of vertically stacked nanosheet CFET and standard CMOS without and with parasitic channels

The threshold voltage regulation and the effect of parasitic channels are important issues in CFET. In this paper, the characteristics of the complementary field-effect transistor (CFET) were simulated based on a self-aligned vertically stacked nanosheet fabrication process at the 2 nm technology node by TCAD simulation. The electrical characteristics of CFET were matched by adjusting the metal work function. We analyzed the static characteristics and transient response, as well as the impact of the parasitic channel. Compared to standard CMOS with the same process, the switching threshold and noise margin of CFET are approximately equal to CMOS, but the power and speed are slightly better than CMOS because nFET and pFET of CFET share the same gate to have small parasitic capacitance. With the height of the parasitic channel increasing, the off-state current and parasitic capacitance of the device increase, but CFET suppresses the bad effect of the parasitic channel and changes less. CFET with the stacked nanosheet structure has greater advantages than CMOS, can tolerate the parasitic channel from the fabrication process, and improve performance in the perspective of front-end-of-line (FEOL).

Full two-dimensional ambipolar CFET-like architecture for switchable logic circuits

As the scaling of integrated circuits based on silicon semiconductors becomes increasingly challenging due to the minimum feature size being close to the physical limit, the urgent demand for alternative strategies has fuelled the rapid growth of techniques and material innovations. Here, we report on the fabrication of vertically stacked ambipolar complementary field-effect transistor that is fully composed of two-dimensional materials of WSe2/h-BN/graphene/h-BN/WSe2 heterostructures. The ambipolar feature of the top and bottom WSe2 FET enables a switchable inverter behavior with a favorable voltage gain of up to 75, which can work in both the first and third quadrants. Based on the switchable characteristics, a large voltage swing circuit for single photon avalanche detectors is proposed without any bulky negative-voltage components. This work could open a new pathway for future two-dimensional electronics and ultimate monolithic 3D high-density integration circuits.

Two-dimensional material-based complementary ambipolar field-effect transistors with ohmic-like contacts

Ambipolar field-effect transistors (FETs) possessing both electron and hole carriers enable implementation of novel reconfigurable transistors, artificial synaptic transistors, and output polarity controllable (OPC) amplifiers. Here, we fabricated a two-dimensional (2D) material-based complementary ambipolar FET and investigated its electrical characteristics. Properties of ohmic-like contacts at source/drain sides were verified from output characteristics and temperature-dependent measurements. The symmetry of electron and hole currents can be easily achieved by optimization of the MoS2 or WSe2 channels, different from the conventional ambipolar FET with fundamental issues related to Schottky barriers. In addition, we demonstrated successful operation of a complementary inverter and OPC amplifier, using the fabricated complementary ambipolar FET based on 2D materials.

A Novel Design of Low Power & High Speed FinFET Based Binary and Ternary SRAM and 4*4 SRAM Array

The Conventional Complementary Metal Oxide Semiconductor Field Effect Transistor (CMOSFET) design techniques have limitations in designing the Integrated Circuit (ICs), especially with memories of multiple valued logic (MVL) in nanotechnologies. FinFET technologies provide the possibilities of low logic gates and small chip areas with high speed. Memories play an essential role in all types of devices. This paper aims to optimize the power and increase the speed of the SRAM Cell and Array using different techniques in 18nm FinFET technology. The presence of a ternary input provides an additional degree of freedom for the operation of the memory cell. The SRAM cells are also implemented at a Quantum level to improve the results in terms of area, energy, and speed. Simulation and Analysis of the design is done using Cadence Virtuoso Analog Design Environment Tool and Quantum Dot Cellular Automata Designer Tool. The proposed Multi-Threshold Complementary MOS (MTCMOS) based SRAM Array design exhibits an improvement of 4.56% in power consumption and 19.29% in speed as compared to a Conventional CMOS SRAM Array. The proposed ternary implementation of the MTCMOS-based SRAM cell is found to have a 24.9% reduction in power consumption and a 39% improvement in speed as compared to the proposed conventional ternary CMOS SRAM array while SRAM cell latency is 1 clock cycle. It occupies an area of 0.04 µm2 and consists of 33 quantum cells. The average energy dissipation of this SRAM cell is found to be 40% better than the latest existing literature for the design.

A CNTFET Based Bit-Line Powered Stable SRAM Design for Low Power Applications

Higher charge mobility, gate control, and better electrostatics are the key reasons that make carbon nanotube field effect transistor (CNTFET) a better candidate to become the successor of conventional CMOS transistors. However, the increased charge mobility also enhances the leakage power. This work uses CNTFET for designing a low-power eight-transistor static random access memory (8T SRAM) cell. The leakage power of the proposed cell is reduced by 2.21×compared to conventional 6T SRAM at 0.3V with similar CNTFET parameters. The read and write power delay product of the proposed design is improved by 1.02×and 1.85×, respectively. Moreover, the read/ write/ hold static noise margin of the proposed cell is also enhanced by 1.98×/ 0.99×/ 1.01×, respectively, compared to the conventional 6T design. The proposed cell is also compared with three already proposed CNTFET based 8T SRAM designs. Cadence Virtuoso simulation tool and Stanford University 32 nm CNTFET verilog-A model file are used to achieve simulation results.

CFET SRAM DTCO, Interconnect Guideline, and Benchmark for CMOS Scaling

This article explores and evaluates six-transistor static random access memory (SRAM) bitcell design options for sequential and monolithic complementary field-effect transistors (CFET) in 5-Å-compatible (A5) and 3-Å-compatible (A3) technology. A5 CFET offers up to 55% and 40% SRAM bitcell area scaling due to stacked architecture as compared to 14-Å-compatible (A14) nanosheet (NS) technology and 10-Å-compatible (A10) forksheet (FS) technology counterparts, respectively. A dielectric isolation wall (DIW) between gates is introduced in A3 CFET SRAM as a scaling booster. Replacement of gate-cuts with DIW results in up to 17% bitcell area scaling in A3 as compared to A5 CFET SRAM. However, aggressive area scaling introduces routing complexity and limits the node-to-node power and performance (PP) gain. Thus, the interconnect design guidelines are provided to overcome these challenges for power, performance, and area (PPA) enhancements of high-density (HD) SRAM.