Complementary Thin-film Transistors Research Articles

Compositional Engineering of Cu-Doped SnO Film for Complementary Metal Oxide Semiconductor Technology.

Metal oxide semiconductor (MOS)-based complementary thin-film transistor (TFT) circuits have broad application prospects in large-scale flexible electronics. To simplify circuit design and increase integration density, basic complementary circuits require both p- and n-channel transistors based on an individual semiconductor. However, until now, no MOSs that can simultaneously show p- and n-type conduction behavior have been reported. Herein, we demonstrate for the first time that Cu-doped SnO (Cu:SnO) with HfO2 capping can be employed for high-performance p- and n-channel TFTs. The interstitial Cu+ can induce an n-doping effect while restraining electron-electron scatterings by removing conduction band minimum degeneracy. As a result, the Cu3atom%:SnO TFTs exhibit a record high electron mobility of 43.8 cm2 V-1 s-1. Meanwhile, the p-channel devices show an ultrahigh hole mobility of 2.4 cm2 V-1 s-1. Flexible complementary logics are then established, including an inverter, NAND gates, and NOR gates. Impressively, the inverter exhibits an ultrahigh gain of 302.4 and excellent operational stability and bending reliability.

How to print high-mobility metal oxide transistors—Recent advances in ink design, processing, and device engineering

High-throughput printing-based fabrication has emerged as a key enabler of flexible electronics given its unique capability for low-cost integration of circuits based on printed thin film transistors (TFTs). Research in printing inorganic metal oxides has revealed the potential for fabricating oxide TFTs with an unmatched combination of high electron mobility and optical transparency. Here, we highlight recent developments in ink chemistry, printing physics, and material design for high-mobility metal oxide transistors. We consider ongoing challenges for this field that include lowering process temperatures, achieving high speed and high resolution printing, and balancing device performance with the need for high mechanical flexibility. Finally, we provide a roadmap for overcoming these challenges with emerging synthetic strategies for fabricating 2D oxides and complementary TFT circuits for flexible electronics.

Multi-Segment TFT Compact Model for THz Applications.

We present an update of the Rensselaer Polytechnic Institute (RPI) thin-film transistor (TFT) compact model. The updated model implemented in Simulation Program with Integrated Circuit Emphasis (SPICE) accounts for the gate voltage-dependent channel layer thickness, enables the accurate description of the direct current (DC) characteristics, and uses channel segmentation to allow for terahertz (THz) frequency simulations. The model introduces two subthreshold ideality factors to describe the control of the gate voltage on the channel layer and its effect on the drain-to-source current and the channel capacitance. The calculated field distribution in the channel is used to evaluate the channel segment parameters including the segment impedance, kinetic inductance, and gate-to-segment capacitances. Our approach reproduces the conventional RPI TFT model at low frequencies, fits the measured current–voltage characteristics with sufficient accuracy, and extends the RPI TFT model applications into the THz frequency range. Our calculations show that a single TFT or complementary TFTs could efficiently detect the sub-terahertz and terahertz radiation.

A Fundamental Reason for the Need of Two Different Semiconductor Technologies for Complementary Thin-Film Transistor Operations

In this short commentary, we discuss a fundamental reason why two different semiconductor technologies are needed for complementary thin-film transistor (TFT) operations. It is mainly related to an energy-level matching between the band edge of the semiconductor and the work-function energy of the metal, which is used for the source and drain electrodes. The reference energy level is determined by the energy range of work-functions of typical metals for the source and drain electrodes. With the exception of silicon, both the conduction band edge (EC) and valence band edge (EV) of a single organic or inorganic material are unlikely to match the metal work-function energy whose range is typically from –4 to –6 eV. For example, typical inorganic materials, e.g., Zn–O, have the EC of around –4.5 eV (i.e., electron affinity), so the conduction band edge is within the range of the metal work-function energy, suggesting its suitability for n-channel TFTs. On the other hand, p-type inorganic materials, such as Cu–O, have an EV of around –5.5 eV, so the valence band edge is aligned with metal work-function energy, thus the usage for p-channel TFTs. In the case of p-type and n-type organic materials, their highest occupied molecular orbital (HOMO) and lowest occupied molecular orbital (LUMO) should be aligned with metal work-function energy. For example, p-type organic material, e.g., pentacene, has a HOMO level around –5 eV, which is within the range of the metal work-function energy, implying usage for p-channel TFTs. However, its LUMO level is around –3 eV, not being aligned with the metals’ work-function energy. So it is hard to use pentacene for n-channel TFTs. Along with this, n-type organic materials (e.g., C60) should have HOMO levels within the typical metals’ work-function energy for the usage of n-channel TFT. To support this, we provide a qualitative and comparative study on electronic material properties, such as the electron affinity and band-gap of representative organic and inorganic materials, and the work-function energy of typical metals.

Solution-processed organic-inorganic hybrid gate insulator for complementary thin film transistor logic circuits

In this work, we demonstrated a poly(4-vinylphenol-co-methyl methacrylate) (PVP-co-PMMA)/Al2O3 double-stacked insulator deposited by solution process. The double-stacked insulator exhibited higher degree of performance uniformity than individual single-stacked insulators. We fabricated an inverter circuit in order to demonstrate the applicability of the proposed insulator in complementary logic circuits, which are composed of metal oxide thin film transistors as the n-channel device and organic thin film transistors as the p-channel device. We utilized amorphous indium gallium zinc oxide thin film transistor and pentacene thin film transistor for the n-channel and p-channel devices, respectively. It was observed that the PVP-co-PMMA/Al2O3 double-stacked insulator had the effect of overcoming the problems related to individual single-stacked layers, such as high leakage current of Al2O3 and low dielectric constant of PVP-co-PMMA. The inverter operated at a threshold voltage of 1.5 V and exhibited high voltage gain of 17.3 V/V at the supply voltage of 3 V.

Solution-processed hybrid organic–inorganic complementary thin-film transistor inverter

We investigated hybrid organic–inorganic complementary inverters with a solution-processed indium–gallium–zinc-oxide (IGZO) n-channel thin-film transistor (TFT) and p-channel TFTs using the high-uniformity polymer poly[2,5-bis(alkyl)pyrrolo[3,4-c]pyrrolo-1,4(2H,5H)-dione-alt-5,5-di(thiophene-2-yl)-2,2-(E)-2-(2-(thiophen-2-yl)vinyl)thiophene] (PDVT-10). The IGZO TFT was fabricated at 150 °C for 1 min. It showed a high field-effect mobility of 0.9 cm2·V−1·s−1 and a high on/off current ratio of 107. A hybrid complementary inverter was fabricated by combining IGZO with a PDVT-10 thin-film transistor and its operation was confirmed.

Macroscopic alignment of poly(3‐hexylthiophene) for enhanced long‐range collection of photogenerated carriers

ABSTRACTAn epitaxy‐directing solvent additive 1,3,5‐trichlorobenzene is combined with an off‐center spin‐casting technique to produce poly(3‐hexylthiophene) (P3HT) fibers with uniaxial in‐plane alignment on the centimeter scale. Photoconductive atomic force microscopy (pc‐AFM) is used to characterize planar heterojunction devices assembled from phenyl‐C61 butyric acid methyl ester (PCBM) acceptor and both aligned and unaligned P3HT donor. By varying the relative positions of the laser spot (site of carrier generation) and probe (site of hole extraction), it is found that devices with aligned P3HT exhibit anisotropic and greatly enhanced long‐range photocarrier transport, with nearly 10% of original photocurrent measured 400 µm from the laser spot along the direction parallel to the alignment. Complementary thin film transistor (TFT) measurements reveal a factor of ∼3.5 difference in the hole mobilities parallel and perpendicular to the direction of alignment. Together, these findings highlight the importance of macroscopic alignment as a strategy to overcome the low mobilities of disordered polymer semiconductors.1 © 2015 Wiley Periodicals, Inc. J. Polym. Sci., Part B: Polym. Phys. 2016, 54, 180–188

Anomalous Mobility Improvement in Ultra-Low-Temperature Polycrystalline-Silicon Thin-Film Transistors on Flexible Substrate after Laser Lift-Off Process

This work investigates an improvement in anomalous mobility in high-performance ultra-low-temperature polycrystalline-silicon (ULTPS) thin-film transistors (TFTs) on flexible substrate after laser lift-off process. The experiment results reveal that the improvement was observed in p-type TFTs but not observed in n-type ones. It was contributed to the boron atom has more kinetic energy than phosphorous one during laser lift-off process. Consequently, the effect of slight boron movement is to reduce the effective p-TFT channel length.Electronic devices fabricated on flexible substrates have drawn a lot of attention to recent researches in these years. Transistors on flexible substrates were the hearts of flexible technologies. Many literatures reported the implementing methods including carbon-nano-tubes transistors, amorphous silicon TFTs, amorphous IGZO TFTs, and etc.. Some of them suffered from either high temperature process or poor transistor characteristics. And the most important, some of them suffered from single polarity transistors, such only n-type transistors. A very attractive technology for flexible electronics was using ULTPS TFTs fabricated direct on flexible substrate on carrier glass [1]. It could not only realize large-size manufacturing process but also is compatible with current CMOS LTPS TFTs circuits. Since the ULTPS TFTs on flexible substrates needs to be lift-off from carrier glass, the electrical characteristics between before and after lift-off process should be studied. However, there were lacks of study of anomalous mobility improvement in p-channel ULTPS TFTs after laser lift-off process. In this experiment, the complementary ULTPS TFTs, i.e. n- and p- channel devices, were both fabricated on flexible material coated on carrier glass then lift-off by laser irradiation. The brief fabrication process was as followings. First, the carrier glass was coated by a layer of polyimide film. After curing, the complementary TFTs were fabricated under ultra-low temperature process by fine tune the recipes. Finally, to implement flexible electronic applications, the ULTPS TFTs were lift-off from the carrier glass by virtue of excimer laser irradiation. The laser irradiation energy densities were varied to investigate the lift-off process effects on the electrical performance of ULTPS TFTs, as shown in Fig1(a)-(c). One sample, named high-energy laser lift-off (HELLO), was irradiated at 320 mJ/cm2. The other sample, named low-energy laser lift off (LELLO), was irradiated at 300 mJ/cm2. And the device dimension was W/L=20um/4.5um for both n- and p- channel TFTs. As fabricated, the HELLO TFTs have been demonstrated the field-effect electron and hole mobility of 82 and 85 cm2/V-s, respectively, while the corresponding characteristics were 78 and 86 cm2/V-s for the LELLO TFTs. Both of them had the similar performance on carrier glass. After laser lift-off process, it was observed that the electron mobility were 81 and 77 cm2/V-s for HELLO and LELLO devices, accordingly. The hole mobility for LELLO TFTs was 88 cm2/V-s. In the contrast, that for HELLO TFTs was improved to 92 cm2/V-s. It could be seen that the electron mobility was not improved for both HELLO and LELLO devices. And no improvement in hole mobility was observed in LELLO devices, but on the contrary an anomalous hole mobility improvement was found in HELLO devices. In the meanwhile, no significant changes were observed in the other electrical parameters, such as threshold voltage and subthreshold swing[2]. The anomalous field-effect hole mobility improvement may be resulted from the reduction of interface trap density state and the shrinkage of channel. Since the subthreshold swing reflected the interface trap density state between gate insulator and channel and no changes were found, that interpreted that the interesting improvement was not caused by the reduction of interface trap density. On the other hand, since only the HELLO p-channel exhibited the interesting anomalous improvement, it is believed that the boron atom is lighter than phosphorous and diffused during laser lift-off process. Therefore, the boron diffusion occurred only when the laser lift-off energy density. Consequently, the source and drain dopants, namely boron, were slight diffusing into the channel to reduce effective channel length. In conclusion, we investigated the anomalous improvement in p-channel ULTPS TFTs after the high-energy laser-lift-off process. The hole mobility was improved from 85cm2/V-s to 92cm2/V-s. It is believed that these anomalous phenomena may be contributed to boron diffusion caused reduction of channel length. The ULTSP TFTs are promising to future flexible electronic circuits. Reference [1] ISDRS 2009, December 9-11, 2009, College Park, MD, USA [2] IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 11, NOVEMBER 2010 Figure 1

Fabrication of stacked logic circuits for printed integrated circuits

We have demonstrated NAND and NOR logic circuit operations of stacked-structure complementary thin-film transistors (TFTs) using 6,13-bis(triisopropylsilylethynyl)-pentacene (TIPS-pentacene) and soluble ZnO as active layers. Bottom-gate-type TIPS-pentacene TFTs, as p-channel transistors, were formed on n-channel ZnO TFTs with common gate electrodes. Solution-processed silicone-resin layers were used as gate dielectric and electrical interconnection layers between lower and upper TFTs. The stacked-structure integrated circuits have several advantages such as ease of active layer formation, compact device area per stage, and the short length of the interconnection compared with the planar configuration in a conventional logic circuit.

Enabling Hybrid Complementary-TFTs With Inkjet Printed TIPS-Pentacene and Chemical Bath Deposited CdS

We report the fabrication and device analysis to enable high performance/low-temperature complementary thin-film transistors (CTFTs) with 6, 13-Bis(triisopropylsilylethynyl)-pentacene (TIPS-pentacene) and cadmium sulfide (CdS). Isolated transistors are first studied and then integrated in a fully patterned CTFT structure. N-type TFTs were fabricated using atomic layer deposition HfO2 as gate dielectric, followed by a CdS film deposited by chemical bath deposition at 70 °C. A novel approach that uses a parylene-C hard mask to avoid damage to the CdS n-type semiconductor is introduced. Also, a comparison between the n-type transistor performance using two different metals (Au and Al) for source-drain electrodes is presented. P-type transistors were fabricated using a novel approach that combines photolithography and ink-jet printing processes. TIPS-pentacene is deposited with inkjet printing in the active channel well, which is photolithographically defined. The p-type TFT mobilities ranged from 1.2×10-3 to 1.5×10-2 cm2/V-s, whereas for n-type TFTs mobilities were ~ 10 cm2/V-s. CTFTs with a maximum processing temperature of 150 °C are demonstrated. Inverters with gains of 17 were achieved. This fabrication process is compatible with large area and low-cost technologies for flexible electronics applications.

Integration of a graphene ink as gate electrode for printed organic complementary thin-film transistors

We demonstrate a new electrode gate based on graphene ink for complementary printed organic metal oxide semiconductor (CMOS) technology on flexible plastic substrates. The goal is to replace the standard silver electrode gate. Devices made with graphene were enhanced and showed a high field-effect mobility of 3cm2V−1s−1 for P-type and 0.9cm2V−1s−1 for the N-type semiconductors. The improvement is attributed to the increase of the electrical capacitance of the organic dielectric (CYTOP) due to the graphene layer. A seven-stage ring oscillator was made with high oscillation frequencies of 2.1kHz at 40V corresponding to a delay/gate value of 34μs. These performances are promising for use of low cost printed electronic applications.

Complementary integrated circuits on plastic foil using inkjet printed n- and p-type organic semiconductors: Fabrication, characterization, and circuit analysis

Complementary thin-film transistor circuits composed of 6,13-bis(triisopropyl-silylethynyl) pentacene (TIPS–PEN) and a rylene carboxylic diimide derivative for p- and n-channel thin-film transistors (TFTs) were fabricated on flexible foils. The so-called staggered TFT configuration is used, meaning that the semiconductors layers are deposited last. The work-function of the injecting gold electrodes were modified using several self-assembled monolayers (SAMs). For optimized contacts the mobility of the n- and p-channel TFTs was 0.5cm2/Vs and 0.2cm2/Vs, respectively. Strongly degraded performance is obtained when the n-channel material was printed on contacts optimized for the p-channel TFT, and vice versa. This illustrates that for CMOS circuits we need careful work-function engineering to allow proper injection for both electrons and holes. We show for the first time that by using a bimolecular mixture for the SAM we can systematically vary the work function, and demonstrate how this affects the performance of discrete n-type and p-type transistors, as well as CMOS inverters and ring oscillators. Under optimal processing conditions we realized complementary 19-stage ring oscillators with 10μs stage delay operating at 20V.

Organic/oxide hybrid complementary thin-film transistor inverter in vertical stack for logic, photo-gating, and ferroelectric memory operation

We demonstrated a vertically stacked complementary thin-film transistor inverter (VS-CTFT inverter) for the purpose of maximizing potentials beyond logic applications by including photo-gating and ferroelectric memory operation with properly selected organic and oxide materials. For our VS-CTFT inverter for logic and photo-gating, we used a thermally-evaporated p-channel pentacene layer, sputter-deposited n-channel GaZnSn-based oxide (GZTO), and atomic layer deposited (ALD) Al 2O 3 dielectric. As a more advanced hybrid approach, we also adopted a ferroelectric poly(vinylidene fluoride/trifluoroethylene) [P(VDF–TrFE)] layer for a CTFT nonvolatile memory inverter with a pentacene memory TFT which is vertically stacked on a top-gate GZTO TFT. Our VS-CTFT inverter nicely displays effective photo- and electrical-gating with a high voltage gain, dynamically operating in the low-voltage regime of 3, 5, and 8 V. The ferroelectric memory inverter as an ultimate hybrid device form demonstrates promising retention properties as triggered by ±20 V gate pulses.

Development of a hybrid inverter through integration of organic and inorganic thin film transistors

In this paper, complementary thin-film transistor (TFT) inverter is fabricated with organic–inorganic hybrid channels. By adopting p-channel pentacene and n-channel ZnO, we have fabricated a device of hybrid complementary TFT inverter by using same electrode in organic–inorganic hybrid channels. To be accomplished Ohmic-contact in organic–inorganic hybrid channels, we adapted to n-channel staggered TFT and p-channel coplanar TFT. In results, a hybrid inverter built through integration of organic and inorganic TFT shows that the typical inverter response to stage switching is clearly observed between 0 and 40 V, for both input directions, displaying a high voltage gain — (d V OUT/d V IN) > 16.

Process and Characterization of Hybrid-Oriented Complementary Single-Crystal Si Thin-Film Transistors on A Plastic Substrate

We report the first flexible single-crystal Si complementary thin-film transistors (TFTs) based on hybrid-orientation technology (HOT) fabricated on plastic substrate. Silicon nanomembranes (SiNMs) from Si (001) and (110) source SOI wafers were integrated onto one plastic substrate. The complementary inverters consist of n-TFTs with a channel direction along Si (110)/<110> aligned side-by-side with p-TFTs along (001)/<110>, The gate lengths of both devices are 5 μm and gate widths are 15 μm and 30 μm for n- and p-TFTs respectively. Typical field-effect transistor performances were achieved from individual n- and p-TFTs. This work shows the potential hybrid inverters composed of n-TFTs along Si (001)/<110> and p-TFTs along (110)/<110>, which is believed to have an enhanced switching speed.

Transparent Photo‐Stable Complementary Inverter with an Organic/Inorganic Nanohybrid Dielectric Layer

AbstractTransparent electronics has been one of the key terminologies forecasting the ubiquitous technology era. Several researchers have thus extensively developed transparent oxide‐based thin‐film transistors (TFTs) on glass and plastic substrates. However, work in transparent electronics has been limited mostly to high‐voltage devices operating at more than a few tens of volts, and has mainly focused on transparent display drivers. Low‐voltage logic devices, such as transparent complementary inverters, operating in an electrically stable and photo‐stable manner, are now very necessary to practically realize transparent electronics. Electrically stable dielectrics with high strength and high capacitance must also be proposed to support this mission, and simultaneously these dielectrics must be compatible with both n‐ and p‐channel TFTs in device fabrication. Here, a nanohybrid dielectric layer that is composed of multiple units of inorganic oxide and organic self‐assembled monolayer is proposel to support a transparent complementary TFT inverter operating at 3 V.

Pentacene and ZnO hybrid channels for complementary thin-film transistor inverters operating at 2V

We report on the fabrication of complementary thin-film transistor (TFT) inverter with organic-inorganic hybrid channels. By adopting organic-pentacene p channel and inorganic-ZnO n channel, we have fabricated a model device of hybrid complementary TFT inverters at a low channel deposition temperature below 100°C. Although those p and n channels were deposited on high-temperature-processed thin gate oxide/p-Si here, our complementary device demonstrated good potentials toward air-stable logic applications, operating with an excellent voltage gain of ∼26 at 2V as well as with a dynamic response of ∼10ms.

Bias Temperature Instabilities for Low-Temperature Polycrystalline Silicon Complementary Thin-Film Transistors

The degradation mechanisms of both negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) were studied for low-temperature polycrystalline silicon complementary thin-film transistors. Measurements show that both NBTI and PBTI are highly bias dependent; however, the effect of the temperature is only functional on the NBTI stress. Furthermore, instead of interfacial trap-state generation during the NBTI stress, the PBTI stress passivates the interface trap states. We conclude that the diffusion-controlled electrochemical reactions dominate the NBTI degradation while charge trapping in the gate dielectric controls the PBTI degradation.

Low voltage complementary thin-film transistor inverters with pentacene-ZnO hybrid channels on AlOx dielectric

The authors report on the fabrication of complementary thin-film transistor (CTFT) inverters with pentacene (p type) and ZnO (n type) hybrid channels on rf-deposited AlOx dielectrics. All deposition processes were carried out on glass substrates at low temperatures (&amp;lt;100°C). Since our p-channel TFT showed somewhat equivalent field mobility of 0.11cm2∕Vs compared to that of the n-channel device (0.75cm2∕Vs), the hybrid CTFT inverters were designed with identical dimensions for both channels. The CTFT device demonstrated an excellent voltage gain of ∼21 with a low static power dissipation of ∼1.5nW at a low supply voltage of 7V.

A Novel Approach to Compact Model Parameter Extraction for Excimer Laser Annealed Complementary Thin Film Transistors

A unified physical-based model parameter extraction technique for excimer laser annealed lower temperature polycrystalline silicon (LTPS) complementary thin film transistors (TFTs) is for the first time proposed. For two well-known compact models of LTPS TFT, Rensselaer Polytechnic Institute (RPI) V1 and V2 models, our approach sequentially optimizes the model parameters in the regions of linear, subthreshold, saturation, and leakage. Compared with the measured results, the extracted I D −V G , I D −V D , transconductance, and output conductance are within 3% of accuracy. The agreement with the experimental data is excellent for the n- and p-type LTPS TFTs with different length and width. This extraction technique bridges the fabrication of LTPS TFTs and the design of complementary system on panel circuits.