Complementary Metal Oxide Semiconductor Logic Research Articles

Numerical investigation of diamond complementary logic integrated circuits

Silicon complementary metal oxide semiconductor (CMOS) technology drives the integrated circuit industry due to its energy efficiency. The narrow bandgap of silicon has led to the development of wide bandgap semiconductor materials, such as diamond, favored in power electronics, radiofrequency and extreme environment applications. Here we have established a model of the diamond CMOS logic inverter for the first time and successfully simulated the static and dynamic characteristics. The simulated physical model and relevant model parameters are well calibrated with experimental data of diamond p-FET in the literature. The simulation results demonstrate that the all-diamond CMOS inverters possess rail-to-rail operation and excellent inversion characteristics, with the peak gain of 83 V/V, the transition region of 0.25 V, and the noise margins for low and high level of 2.44 V and 2.26 V under VDD = 5 V. Particularly, all-diamond CMOS inverters have improved performance compared to the diamond-GaN inverters, operating at 500 °C with well-preserved inversion characteristics. This thermal reliability indicates that diamond CMOS inverters can be better monolithically integrated for applications in high-temperature environments in the future.

Electrical Polarity Modulation in V-Doped Monolayer WS2 for Homogeneous CMOS Inverters.

As demand for higher integration density and smaller devices grows, silicon-based complementary metal-oxide-semiconductor (CMOS) devices will soon reach their ultimate limits. 2D transition metal dichalcogenides (TMDs) semiconductors, known for excellent electrical performance and stable atomic structure, are seen as promising materials for future integrated circuits. However, controlled and reliable doping of 2D TMDs, a key step for creating homogeneous CMOS logic components, remains a challenge. In this study, a continuous electrical polarity modulation of monolayer WS2 from intrinsic n-type to ambipolar, then to p-type, and ultimately to a quasi-metallic state is achieved simply by introducing controllable amounts of vanadium (V) atoms into the WS2 lattice as p-type dopants during chemical vapor deposition (CVD). The achievement of purely p-type field-effect transistors (FETs) is particularly noteworthy based on the 4.7 at% V-doped monolayer WS2, demonstrating a remarkable on/off current ratio of 105. Expanding on this triumph, the first initial prototype of ultrathin homogeneous CMOS inverters based on monolayer WS2 is being constructed. These outcomes validate the feasibility of constructing homogeneous CMOS devices through the atomic doping process of 2D materials, marking a significant milestone for the future development of integrated circuits.

Wafer‐Scale CMOS‐Compatible Electro‐Thermally Actuated Nanomechanical Non‐Volatile Switch with Out‐of‐Plane Electrode Configuration

AbstractThe rapid growth of data‐intensive applications has significantly heightened the concerns about power consumption in current computing systems. From this perspective, there have been substantial efforts to implement ultra‐low power systems by integrating nanoelectromechanical non‐volatile switches (NEM‐NVS) with near‐zero leakage current into standard complementary metal‐oxide‐semiconductor (CMOS) circuits. To practically harness the potential of the NEM‐NVS, it is imperative to achieve high performance, such as low voltage, high on/off ratio, and high reliability, while simultaneously ensuring wafer‐scale CMOS compatibility. However, achieving these requirements is still challenging, primarily due to their electrostatic operation, in‐plane electrode configuration, and conventional fabrication methods. Here, an electro‐thermally actuated nanomechanical non‐volatile switch (ETAN‐NVS) with an out‐of‐plane electrode configuration along with an 8‐inch wafer‐scale CMOS‐compatible fabrication method is reported. By introducing the electrothermal mechanism into a vertically actuated buckling nanostructure, the fabricated ETAN‐NVS attains CMOS‐level voltage (<2.4 V), a high on/off ratio (>108), and exceptional reliability (>1300 cycles). Moreover, a successful wafer‐scale demonstration of the ETAN‐NVS using only a CMOS‐compatible process paves the way for 3D integration with CMOS logic.

Sequential Circuits Synthesis for Rapid Single Flux Quantum Logic Based on Finite State Machine Decomposition

Rapid Single Flux Quantum (RSFQ) logic is a promising technology to supersede Complementary metal-oxidesemiconductor (CMOS) logic in some specialized areas due to providing ultra-fast and energy-efficient circuits. To realize a large-scale integration design, electronic design automation (EDA) tools specialized for RSFQ logic are required due to the divergences in logic type, timing constraints, and circuit structure compared with CMOS logic. Logic synthesis is crucial in converting behavioral circuit description into a circuit netlist, typically combining combinational and sequential circuit synthesis. For the RSFQ logic, the sequential circuit synthesis is challenging, especially for non-linear sequential blocks with feedback loops. Thus, this paper presents a sequential circuit synthesis algorithm based on finite state machine (FSM) decomposition, which ensures design functionality, lowers costs, and improves the RSFQ circuit performance. Additionally, we present the synthesis processes of the feedback logic and the 2-bit counter to demonstrate how the proposed algorithm operates, and ISCAS89 benchmark circuits reveal our method’s ability to synthesize large-scale sequential circuits.

Design and Validation of a V-Gate n-MOSFET-Based RH CMOS Logic Circuit with Tolerance to the TID Effect

This study designed a radiation-hardened (RH) complementary metal oxide semiconductor (CMOS) logic circuit based on an RH variable-gate (V-gate) n-MOSFET that was resistant to the total ionizing dose (TID) effect and evaluated its tolerance to radiation. Among the different CMOS logic circuits, NOT, NAND, and NOR gates were designed using V-gate n-MOSFETs by employing layout transformation techniques and standard p-MOSFETs. Before the process design, we predicted the radiation damage using modeling and simulation techniques and validated the tolerance by conducting actual radiation tests after the process design. Furthermore, we implemented the CMOS logic circuit process design in a 0.18 µm CMOS bulk process. The actual radiation test applied a total cumulative radiation dose of 25 kGy at 5 kGy per hour in a high-level gamma-ray irradiation facility. Consequently, the resistance of the RH CMOS logic circuit based on the RH V-gate n-MOSFET to the TID effect was validated through experiments.

Ultra‐Flexible Monolithic 3D Complementary Metal‐Oxide‐Semiconductor Electronics

AbstractFlexible electronics based on complementary metal‐oxide‐semiconductor (CMOS) technology have enabled a smart soft world. However, the trade‐off among flexibility, density, and electrical performance has been a long‐lasting unresolved issue. Here, a monolithic three‐dimensional (M3D) CMOS design is proposed to address this problem and realize ultra‐flexible electronics with high electronic‐performance and integration. This design utilizes vertically stacked p‐type carbon nanotube transistors and n‐type indium gallium zinc oxide ones, which share common gates and drains, saving the inter tier vias required in the traditional M3D structure to reduce routing and improve flexibility. With this design, CMOS logic gates, multi‐stage circuits, ring oscillators (ROs) and memory modules, are demonstrated. This design enables circuits to save up to 45% of area compared with their planar counterparts. Particularly, inverters exhibit a record‐high gain of 191, and 55‐stage ROs can operate well even after bending at a 500‐µm radius for 50 cycles, exhibiting the highest flexibility among the reported ones. The ultra‐flexible and high‐integration RO enables a wearable light recorder to collect harmful blue light shining into human eyes by simply attaching the circuits on a contact lens. This integration method provides possibilities for developing complex‐function wearable electronics.

ALUSGDI: Low power arithmetic logic unit based sliced processor using GDI and MGDI

In recent years, many digital logic circuits in terms of transistors such as Pass Transistor Logic (PTL), Complementary Metal Oxide Semiconductor (CMOS) logic and etc. have been used for implementing DSP algorithms. Gated Diffusion Input (GDI) logic is also another method for implementing digital circuits. In this work, GDI logic style is used in the proposed ALU based Filter Bank. The ALU unit of the proposed filter bank is designed by modified GDI logic. Power consumption of the entire design is also reasonably reduced using recursive parallel self-timed adder. GDI logic has three terminals which are Common Gate (G), PMOS (P)/NMOS (N) and output terminal. The number of transistors is reduced when compared to Complementary Metal Oxide Semiconductor (CMOS) logic. Hence, the reduced number of transistors eliminates the switching activity and power dissipation. The GDI logic consumes 65% less area and 91.4% less power when compared to CMOS logic. The modified GDI logic provides 77.5% area reduction when compared to CMOS logic. The experimental results obtained using the proposed ALU based Sliced Processor by employing GDI logic compared with the traditional filter bank techniques. ALU based filter bank design speeds up significantly through GDI concepts when compared to the interpolated filter bank and the design is implemented in 65 nm CMOS technology.

Integrated Low‐Dimensional Semiconductors for Scalable Low‐power CMOS Logic

AbstractScalable nanoelectronics with energy‐efficient logic technology is crucial for next‐generation edge devices. Low‐dimensional semiconductors, such as transition metal dichalcogenides and single‐walled carbon nanotubes (SWCNTs), have tunable properties with reduced short‐channel effects. The unique properties of each material can be utilized owing to the heterogeneous integration of multiple semiconducting channels to form complementary metal‐oxide‐semiconductor (CMOS) logic. However, the integration remains challenging. This study reveals the realization of low static power hetero‐CMOS inverters by the integration of n‐type monolayer MoS2 and p‐type SWCNT networks. The balanced inverter exhibits a large peak gain of ≈67 at a supply voltage of 2 V with the customized design of the wafer‐scale synthetic process and channel integration. An ultralow standby power consumption of ≈5 pW and a practical peak gain of ≈7 at a reduced supply voltage of 0.25 V are achieved. A high noise margin (>70%) validates the circuit's tolerance to external noises and the dynamic analysis of the inverting amplifier in push–pull configuration exhibits a large AC gain. This work paves the way toward the wafer‐scale integration of low‐dimensional materials for low‐power nanoelectronics.

A low power design using FinFET based adiabatic switching principle: Application to 16-Bit arithmetic logic unit

This paper presents a novel 16-bit arithmetic logic unit (ALU) design by cascading simple 1-bit ALUs using metal–oxide-semiconductor field effect transistor (MOSFET) and FinFET technologies while incorporating adiabatic switching principle. Analyses are carried out at 32 nm Berkley predictive technology module (PTM). The paper has employed popular standard adiabatic logic families– such as quasi-static energy recovery logic (QSERL), two phase drive adiabatic dynamic complementary metal oxide semiconductor (CMOS) logic (2PADCL), adiabatic dynamic CMOS logic (ADCL), and two phase clocked adiabatic static CMOS logic (2PASCL). Single-phase adiabatic logic circuit is also introduced. Results show that the proposed technique has power savings of 67.14 %, 39.47 %, 34.65 %, 8.73 %, and 4.16 % for CMOS, QSERL, 2PADCL, ADCL, and 2PASCL respectively with MOSFET technology whereas, it saves 95.22 %, 21.34 %, 20.75 %, 15.66 %, and 8.69 % respectively for same literatures with FinFET technology.

A power efficient fully adiabatic logic circuit design approach: application to inverter and 8421 to excess-3 code converter

Decreasing power consumption is the leading challenge for very-large-scale-integrated (VLSI) designers. This paper introduces an innovative prototype for a power-efficient standard or a fully-adiabatic binary-coded-decimal (BCD) 8421 to Excess-3 (XS-3) code converter. The proposed design is compared with traditional complementary metal oxide semiconductor (CMOS) as well as two popular fully adiabatic logic families: adiabatic dynamic CMOS logic (ADCL) and two phase clocked adiabatic static CMOS logic (2PASCL). This investigation was conducted at frequencies ranging from 100 to 900 MHz. The circuit employs 0.3 μm CMOS technology, with channel length and width set at 0.3 μm and 0.75 μm, respectively. The power savings for the proposed logic at 500 MHz when compared to standard CMOS logic, ADCL, and 2PASCL are 54.54%, 28.57%, and 16.67%, respectively.

Cu2O p-type Thin-Film Transistors with Enhanced Switching Characteristics for CMOS Logic Circuit by Controlling Deposition Condition and Annealing in the N2 Atmosphere

Cuprous oxide (Cu2O) p-type thin-film transistors (TFTs) can be practically applied for complementary metal oxide semiconductor (CMOS) logic circuits, but the electrical performances are still insufficient due to high off-current and low field-effect mobility. Here, we have demonstrated Cu2O TFTs with improved field-effect mobility and low off-current through reduction of cupric oxide (CuO) impurities and dissociative Cu defects with the combination of deposition and annealing conditions. Copper oxide was deposited by radio frequency sputtering in mixed gases of argon and oxygen. After that, the deposited copper oxide was annealed at 800 °C in the tube furnace under a N2 atmosphere instead of a high vacuum condition. The fabricated Cu2O thin film had a high crystalline quality, the ratio of dissociative Cu defects decreased from 11.3 to 3.1%, and the electrical performances of the TFT including the fabricated Cu2O thin film exhibited the field-effect mobility of 1.11 ± 0.05 cm2/V·s, the on/off current ratio of 4.68 ± 0.8 × 104, and the subthreshold swing value of 3.91 ± 0.21 V dec–1. The fabricated Cu2O TFT showed a Vth shift of 3.31 V in the transfer curve under negative bias stress. Nitrogen plays a role in promoting Cu2O phase formation while it prevents CuO phase formation during the annealing process. In addition, oxygen added during sputtering increases the ratio of CuO in the copper oxide thin film and works effectively to reduce dissociative Cu defects in the annealing process. To determine the feasibility of the CMOS logic circuit, we also demonstrated the inverter with n-type indium–gallium–zinc oxide (IGZO) TFT and p-type Cu2O TFT, which showed a voltage gain of 14 at VDD = 20 V.

An Online Course Content for Undergraduate Students on Full-Custom Design of a Digital VLSI Circuit Using Open-Source Software

The Very Large-Scale Integration (VLSI) circuit design is a promising field for undergraduate students hoping to explore job opportunities in electronics circuit design companies. Therefore, several institutes in India offer VLSI courses to electronics engineering undergraduate students. In recent times, because of the pandemic, online classes appeared as an effective method of teaching; this helped in running of academic schedule smoothly without hampering the students’ learning process. In this paper online teaching content is presented to help the student learn digital VLSI circuit design using an open-source tool. This course content is particularly helpful in understanding the theoretical and practical design of a Complementary Metal Oxide Semiconductor (CMOS)-based logic function, with minimal effort by the faculty without access to campus software. The content starts with a digital logic function and its switch-level representation into PULL-UP and PULL-DOWN networks. Then the switch-level circuit with the help of Euler’s graph is translated into a stick diagram and then converted into a layout cell using the lambda design rule. An interesting approach to choosing the gate sequence in the stick diagram from Euler’s graph, and the simulation result of the layout cell are presented and discussed. The approach helped the students in understanding full custom CMOS logic function design, test, and validation, with less effort and time. The survey shows that 86% of the students were satisfied with the content and that the course content helped to achieve an 81% average pass percentage in the two online semesters.

Energy-Efficient circuits with improved diode free adiabatic logic design methodology

This paper demonstrates a detailed analysis of an unique improved diode-free adiabatic logic (IDFAL) circuit. The IDFAL is operated based on adiabatic switching principle. To indicate the circuit effectiveness, numerous analyses are carried out on different complementary metal oxide semiconductor (CMOS) technology nodes. Logic circuits, viz., NOT and NAND are analyzed and simulated using the traditional CMOS design style and some popular adiabatic logic design techniques: two-phase clocked adiabatic static CMOS logic (2PASCL), diode free adiabatic logic (DFAL), adiabatic dynamic CMOS logic (ADCL), two-phase adiabatic dynamic CMOS logic (2PADCL), quasi-static energy recovery logic (QSERL), and clocked CMOS adiabatic logic (CCAL). The results are compared with the proposed design (IDFAL) at various operating frequencies. The results revealed that the IDFAL inverter circuit has the least power delay product (PDP) among the reported adiabatic design methodologies and saves 91.59 % over the counter-part CMOS inverter at 16 nm high-performance predictive technologies (HP_PTM).

Investigation of p-type High Temperature Field Effect Transistor for CMOS Logic Application

In this study, we propose a silicon-based metal oxide semiconductor field effect transistor (MOSFET) device for p-type that can operate at a high temperature (at 573 K). This device can be applied to logic circuits, and furthermore, used in semiconductor chips operating in high temperature environments. Through research, we selected 3C-SiC, which can prevent off-current most effectively, as a material to be applied to the device. After that, technology computer aided design (TCAD) simulation will be used to apply the interface characteristics according to the physical properties of silicon and 3CSiC, and to optimize the current characteristics of device as a logic element. In addition, we investigated a complementary metal oxide semiconductor (CMOS) logic circuit with simulation program with integrated circuit emphasis (SPICE) and verify the inverting characteristics in a high temperature environment of 573 K by applying the device of this study.

(Invited) Achieving Lower Power Logic Using P-Type Metal Oxide Thin Film Transistors

Thin film transistors (TFTs) have enabled the active matrix displays that are a ubiquitous part of everyday life, from mobile phones and tablets through to desktop monitors and home televisions. They are used in the circuit at each pixel over the display as they can be fabricated for relatively low cost with excellent uniformity at low temperatures over large areas on glass substrates. These pixel circuits only require either n-channel or p-channel enhancement mode TFTs. However, there has long been a desire to integrate the display driver electronics onto the display panel as an alternative to connecting silicon-based integrated circuits using complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) to displays. More recently, there has been an increasing interest in producing other logic circuits using TFTs on glass and plastic substrates as this could enable a new generation of products with embedded electronics. However, both of these applications need low power logic circuits. CMOS is an inherently low power technology, but it requires both n-channel and p-channel transistors. Whilst this can be realised in silicon CMOS FETs, it has not yet been achieved using TFTs because it has proved difficult to realise both n-channel and p-channel devices using one material system at low cost. For example, hydrogenated amorphous silicon can be used to make reasonable n-type material but not p-type.Thin film oxide semiconductors such as amorphous indium gallium zinc oxide have been successfully commercialised in the pixel circuits of active matrix displays as they possess high field effect mobility, low threshold voltage, low off-state current and a high switching ratio. There is therefore a lot of interest in finding a suitable complementary p-type metal oxide thin film material to allow CMOS-type logic to be realised using this material system.Cuprous oxide is one such promising candidate material as the top of the valence band is dominated by states which form as a result of hybridisation of the completely filled Cu 3d orbitals and the O 2p orbitals. These hybridised states are less localised and have a higher dispersion with a resulting decrease in the effective mass of holes in these states and a higher carrier mobility. The results of an extensive study of this material shows that the grain structure is of critical importance with [100] oriented films resulting in a higher mobility. Furthermore, the impact of grain boundaries on conduction must be controlled. Although this allows TFTs with reasonable on-state current to be fabricated, it is found that there is a significant residual off-state current which is a result of electron accumulation in the channel. This is consistent with the high off-state current that has been observed widely in TFTs using p-type metal oxide thin film materials.The low off-state current in silicon MOSFETs means that the geometric transistor design in low power CMOS logic circuits only needs to focus on the effect of the on-state current in the p-channel and n-channel transistors. However, in TFTs, the much larger off-state current also becomes important as it can end up being a significant parameter when calculating the power consumption of CMOS logic circuits. An alternative geometric design parameter for TFT logic circuits is presented. This compares the maximum switching current with the static currents allowing optimisation based on both the noise margin and static power consumption. The result is improved performance of TFT-based CMOS logic circuits using the n- and p-type thin film oxide semiconductors that are currently available.

Comparison of Power Efficient Inverter Circuit using adiabatic technique

The power decadence in conventional CMOS (Complementary Metal oxide Semiconductor) circuit can be diminished by utilizing adiabatic method. Working of Adiabatic logic depends on switching activities, which diminishes the power by giving energy dissipated as heat back to supply. Adiabatic word has come from thermodynamic framework which says that no heat transfer take place from framework to climate as well as the other way around. Adiabatic logic is well known as energy recovery logic because its main objective is to reuse energy. It reuses the energy back to the power supply along the lines diminishing the power dissipation. Adiabatic procedures depend on adiabatic logic guideline. Anu Priya has propose the technique in 2014 [3], of adiabatic procedure where energy dissipation in PMOS organization can be limited and some of energy dissipated at load capacitance can be reused rather than dispersed as heat. Yet, the adiabatic method is exceptionally reliant upon parameter variation. Expecting completely adiabatic activity from a circuit is practically not possible as it is an ideal condition, also adiabatic technology is highly dependent on parameter variations so it’s quite difficult to achieve and ideal adiabatic circuit. It could be just accomplished with extremely sluggish exchanging speed. In examination, three logic families, ECRL (Efficient Charge Recovery Logic), PFAL (Positive Feedback Adiabatic Logic) and CPAL (Complementary Pass Transistor Adiabatic Logic) are contrasted and conventional CMOS logic for inverter circuit. MICROWIND technology is used while investigating different adiabatic circuits; energy utilization is broke down by variety of parameter. Result shows that adiabatic strategy is better decision in case of underpowered application in explicit frequency range.

Demonstration of PdSe2 CMOS Using Same Metal Contact in PdSe2 n‐/p‐MOSFETs through Thickness‐Dependent Phase Transition

AbstractIn this study, PdSe2 n‐ and p‐metal‐oxide semiconductor field‐effect transistors (MOSFETs) are realized using the same conventional metal contact without any doping processes through utilizing the thickness‐dependent phase transition in PdSe2. PdSe2 is semiconducting with a sizable band gap in a few layers while semimetallic in bulk. With the thin semiconducting PdSe2 for the channel and the conventional metal source/drain, an n‐type behavior is achieved, whereas a p‐type behavior with the thin PdSe2 channel and the thick semimetallic PdSe2 source/drain. To understand the carrier injection at the interface between the thin PdSe2 channel and the thick PdSe2 source/drain, a rigorous analysis of the band alignment and the temperature‐dependent transfer characteristics is presented to extract the Schottky barrier height at the interface. Additionally, interconnecting PdSe2 n‐ and p‐MOSFETs successfully demonstrate complementary metal‐oxide semiconductor (CMOS) inverter with clear voltage transfer characteristics. The proposed approach to control the polarity of PdSe2 MOSFETs using the unique thickness‐dependent phase transition in PdSe2 is promising for realizing the CMOS logic circuit with the same channel material and single contact metal.

Power and Area Efficient Cascaded Effectless GDI Approximate Adder for Accelerating Multimedia Applications Using Deep Learning Model

Approximate computing is an upsurging technique to accelerate the process through less computational effort while keeping admissible accuracy of error-tolerant applications such as multimedia and deep learning. Inheritance properties of the deep learning process aid the designer to abridge the circuitry and also to increase the computation speed at the cost of the accuracy of results. High computational complexity and low-power requirement of portable devices in the dark silicon era sought suitable alternate for Complementary Metal Oxide Semiconductor (CMOS) technology. Gate Diffusion Input (GDI) logic is one of the prompting alternatives to CMOS logic to reduce transistors and low-power design. In this work, a novel energy and area efficient 1-bit GDI-based full swing Energy and Area efficient Full Adder (EAFA) with minimum error distance is proposed. The proposed architecture was constructed to mitigate the cascaded effect problem in GDI-based circuits. It is proved by extending the proposed 1-bit GDI-based adder for different 16-bit Energy and Area Efficient High-Speed Error-Tolerant Adders (EAHSETA) segmented as accurate and inaccurate adder circuits. The proposed adder's design metrics in terms of delay, area, and power dissipation are verified through simulation using the Cadence tool. The proposed logic is deployed to accelerate the convolution process in the Low-Weight Digit Detector neural network for real-time handwritten digit classification application as a case study in the Intel Cyclone IV Field Programmable Gate Array (FPGA). The results confirm that our proposed EAHSETA occupies fewer logic elements and improves operation speed with the speed-up factor of 1.29 than other similar techniques while producing 95% of classification accuracy.

Surface-engineered Mo2C: an ideal electrode for 2D semiconductor-based complementary circuit with Schottky-barrier-free contacts

The achievement of complementary metal-oxide-semiconductor (CMOS) logic functions and the elimination of Schottky barrier (SB) in two-dimensional (2D) field-effect transistors (FETs) remain critical challenges. Here, by first-principles calculation, a novel straightforward strategy has been provided to achieve CMOS logic functions and SB-free contacts simultaneously in 2D FETs through modifying the surface electrical structure of Mo2C electrode with different groups. Both Mo2C with surfaces fully saturated by O (Mo2CO2) and OH (Mo2C(OH)2) groups are energetically and dynamically stable. Importantly, the interfaces between 2D layered semiconductors (2DLSCs) and Mo2C with fully saturated surfaces show van der Waals contacts, effectively suppressing the Fermi level pinning, making the SB can be modulated by adjusting the work function of electrode. Therefore, Mo2C(OH)2 likely forms n-type contacts with 2DLSCs because of its ultralow work function, whereas Mo2CO2 prefers to form p-type contacts with 2DLSCs because of its ultrahigh work function. Remarkably, all Mo2C(OH)2/2DLSCs and Mo2CO2/2DLSCs systems can form Ohmic contacts. Through this novel strategy, the zero SB height in 2D FETs and the controllable contact polarity (n-type or p-type) in CMOS logic functions can be achieved readily. This work illustrates a novel and powerful method for developing high-performance 2D semiconductor-based complementary circuit.

Ultrafast and Ultralow‐Power Voltage‐Dominated Magnetic Logic

To solve the von Neumann performance bottleneck, many kinds of magnetic logic devices are proposed. However, the operation speed, power consumption, and error rate of these devices are incompatible with complementary metal−oxide−semiconductor (CMOS) logic, and moreover, cascading of the devices is difficult. Herein, instead, a new voltage‐dominated magnetic logic‐memory device is proposed, with switching time of 300 ps and power consumption of 150 fJ, representing ≈10 times improvement compared with CMOS logic on the same scale. The device has a reliable output ratio of >3000%, a low working magnetic field of <10 mT, and a low error rate of ≈10−7. Moreover, complex logic operations, such as XOR gates and a full adder, can be realized using this device via cascading. As a result of these advantages, the magnetic logic‐memory device is well suited for practical applications.