Numerical investigation of diamond complementary logic integrated circuits

Abstract

Silicon complementary metal oxide semiconductor (CMOS) technology drives the integrated circuit industry due to its energy efficiency. The narrow bandgap of silicon has led to the development of wide bandgap semiconductor materials, such as diamond, favored in power electronics, radiofrequency and extreme environment applications. Here we have established a model of the diamond CMOS logic inverter for the first time and successfully simulated the static and dynamic characteristics. The simulated physical model and relevant model parameters are well calibrated with experimental data of diamond p-FET in the literature. The simulation results demonstrate that the all-diamond CMOS inverters possess rail-to-rail operation and excellent inversion characteristics, with the peak gain of 83 V/V, the transition region of 0.25 V, and the noise margins for low and high level of 2.44 V and 2.26 V under VDD = 5 V. Particularly, all-diamond CMOS inverters have improved performance compared to the diamond-GaN inverters, operating at 500 °C with well-preserved inversion characteristics. This thermal reliability indicates that diamond CMOS inverters can be better monolithically integrated for applications in high-temperature environments in the future.