Complementary Metal Oxide Semiconductor Transistors Research Articles

A [92.4] FO4(1V), [53.71] Eu(1V) 4-bit absolute-value detector

With the development of modern computers, the integration of chips is getting higher and higher, and as the computing power increases, the energy consumption of chips is also increasing. Therefore, designing and optimizing low-latency and low-energy chips are the goals of many researchers today. At the same time, 4-bit absolute value detector are one of the most basic and important circuits for data storage and processing in chips. This paper designs a 4-bit absolute value detector circuit using Complementary Metal Oxide Semiconductor (CMOS) transistors that can take the absolute value of the input 4-bit signed number and compare it with the threshold value. And it includes the design of its absolute value conversion module and comparator module. By optimizing the circuit structure, the number of logic gates is reduced. By calculating the minimum delay on the critical path, logic gate size and other parameters, the power consumption of the circuit is reduced by adjusting the delay. In conclusion, this paper research can help further optimize the development of chip design industry.

A multichannel thermal bubble-actuated impedance flow cytometer with on-chip TIA based on CMOS-MEMS

Electrochemical impedance spectroscopy (EIS) flow cytometry offers the advantages of speed, affordability, and portability in cell analysis and cytometry applications. However, the integration challenges of microfluidic and EIS read-out circuits hinder the downsizing of cytometry devices. To address this, we developed a thermal-bubble-driven impedance flow cytometric application-specific integrated circuit (ASIC). The thermal-bubble micropump avoids external piping and equipment, enabling high-throughput designs. With a total of 36 cell counting channels, each measuring 884 × 220 μm2, the chip significantly enhances the throughput of flow cytometers. Each cell counting channel incorporates a differential trans-impedance amplifier (TIA) to amplify weak biosensing signals. By eliminating the parasitic parameters created at the complementary metal-oxide-semiconductor transistor (CMOS)-micro-electromechanical systems (MEMS) interface, the counting accuracy can be increased. The on-chip TIA can adjust feedback resistance from 5 to 60 kΩ to accommodate solutions with different impedances. The chip effectively classifies particles of varying sizes, demonstrated by the average peak voltages of 0.0529 and 0.4510 mV for 7 and 14 μm polystyrene beads, respectively. Moreover, the counting accuracies of the chip for polystyrene beads and MSTO-211H cells are both greater than 97.6%. The chip exhibits potential for impedance flow cytometer at low cost, high-throughput, and miniaturization for the application of point-of-care diagnostics.

CMOS plus stochastic nanomagnets enabling heterogeneous computers for probabilistic inference and learning

Extending Moore’s law by augmenting complementary-metal-oxide semiconductor (CMOS) transistors with emerging nanotechnologies (X) has become increasingly important. One important class of problems involve sampling-based Monte Carlo algorithms used in probabilistic machine learning, optimization, and quantum simulation. Here, we combine stochastic magnetic tunnel junction (sMTJ)-based probabilistic bits (p-bits) with Field Programmable Gate Arrays (FPGA) to create an energy-efficient CMOS + X (X = sMTJ) prototype. This setup shows how asynchronously driven CMOS circuits controlled by sMTJs can perform probabilistic inference and learning by leveraging the algorithmic update-order-invariance of Gibbs sampling. We show how the stochasticity of sMTJs can augment low-quality random number generators (RNG). Detailed transistor-level comparisons reveal that sMTJ-based p-bits can replace up to 10,000 CMOS transistors while dissipating two orders of magnitude less energy. Integrated versions of our approach can advance probabilistic computing involving deep Boltzmann machines and other energy-based learning algorithms with extremely high throughput and energy efficiency.

Single ended 12T cntfet sram cell with high stability for low power smart device applications

Static random-access memory (SRAM) is the most prevalent type of memory used in current system-on-chips (SOC). SRAMs built using Complementary metal oxide semiconductor (CMOS) transistors, suffer from low stability and significant power dissipation at nano scale regime [1]. Studies show that the Carbon nanotube field effect transistor (CNTFET) are prominent to use at nano scale region. This article proposes a 12T CNTFET SRAM cell and its performance metrics like power, stability and delay are compared with various other recent SRAM cells by simulating them using CNTFETs. Two Schmitt trigger (ST) based cross coupled inverter arrangement make up the storage cell in the suggested 12T CNTFET SRAM bit cell. ST-based inverter has stacked N-type transistors, which reduces the circuit's leakage and the voltage transfer characteristics (VTC) of ST inverter is also sharper than the other conventional inverters, thereby enhancing the stability performance of the proposed bit cell. The cell also uses feedback cutting transistor and a separate read and write path to further improve the stability performances during read and write modes. The suggested 12T CNTFET SRAM cell shows higher write SNM, hold SNM and read SNM when compared to other state of the art SRAM cells. The read and write delay of the proposed 12T CNTFET SRAM cell is also seen to improve in contrast to the other SRAM designs. The proposed 12T CNTFET SRAM cell when simulated using 32 nm CNTFET at 0.9 V, shows write power, hold power, read power, write delay, read delay, write static noise margin (WSNM), HSNM and read static noise margin (RSNM), as 0.19 nW, 1.61 nW, 3.13 µW, 119 pS, 7.33 pS, 444 mV, 420 mV, 420 mV respectively. The suggested cell is also tested for parametric variations and its performance is also recorded. The proposed cell surpasses all other cells considered as far as power and stability are concerned making it suitable for usage in smart devices like smart bands, smart watches etc. A 32 nm Stanford University model is used to simulate the proposed 12T CNTFET SRAM cell using the HSPICE tool.

Evaluation of 8-bit eDRAM by varying the aspect ratio of the in-cell transistors

Embedded dynamic random-access memories (eDRAM) are widely used in the design of embedded systems for the safeguard of information during their operation. However, since these memories are installed in the same chip as the host system, it is crucial to consider their dimensioning. For this reason, in our work, the aspect ratio width and length (W/L) of complementary metal oxide semiconductor (CMOS) transistors inside 3-transistor logic cells (3T) is diversified to evaluate the effect on electrical behavior with area optimization through the figure of merit (FoM): power consumption-delay product of 8-bit memories with an operating frequency of 8.3 MHz, varying the aspect ratio of transistors inside the cell have been obtained 8.6f as lowest and 152.3f as highest FoM values. Those storage devices have been developed on 0.00085 mm2 using a 180-nm CMOS technology.

A Comparative Analysis of VS-CNTFET and CMOS Based Inverter Circuit

This abstract delves into the comparative exploration between Carbon Nanotube Field Effect Transistors (CNTFETs) and traditional CMOS (Complementary Metal-Oxide-Semiconductor) transistors, with a specific emphasis on digital inverter circuits. Utilizing carbon nanotubes derived from the graphene allotrope, CNTFETs are introduced as a technological advancement, providing advantages such as reduced size and lower power consumption. The investigation centres on the evaluation of the Stanford model, particularly focusing on the Virtual Source Carbon Nanotube Field Effect Transistor. This specific model showcases superior performance, compact dimensions, and decreased power requirements when contrasted with silicon-based MOSFETs. The analytical process involves subjecting virtual source CNTFET inverter circuits and MOSFET-based circuits to testing via the Symica software tool, encompassing the examination of transient response, voltage transfer characteristics, and steady-state power consumption. The outcomes underscore the potential of CNTFETs as promising alternatives in the progression of digital design, offering heightened efficiency and diminished power consumption.

Novel Wet Etchant for Highly Selective Etching of Si1-XGex-Film to Si-Film with Sodium Periodate Oxidant

As the technology node of complementary-metal-oxide-semiconductor (CMOS) transistor has been scaled down to 3 nm, CMOS transistor’s structure has been changed from fin field-effect transistors to gate-all-around field-effect transistors (GAAFETs) to improve the short-channel effects by enhancing gate controllability. In addition, dynamic random-access memory (DRAM) also has been faced the limitation in scaling-down of a capacitor having high aspect ratio and in migrating from 6 to 4F2 cell increasing floating body effects. To overcome the limitation, 3-dimensional (D) DRAM structure having GAA structure has been researched as an alternative structure to the conventional 6F2 cell structure. In fabricating GAAFETs and 3-D DRAM, two major fabrication processes are needed, i) epitaxial growth of Si1-xGex/Si multi-stacks, and ii) selective etching of Si1-xGex films to Si films. For process i), low Ge concentration (<30%) is desirable for reducing stacking faults and defects at the interfaces between Si1-xGex and Si. In addition, for process ii), considerably high etch rate (>30nm/min) and etch selectivity of Si1-xGex films to Si films (>300:1) are required. In particular, for etching Si1-xGex grown on Si layer of a sacrificial layer, a high selectivity, high etch rate and isotropy of wet chemical etching are strongly required. In general, among the components of wet chemical etchant consisting of oxidant, etching accelerator (i.e., HF), selectivity enhancing agent (i.e., acetic acid), and deionized water, the higher standard reduction potential (SRP) of oxidant leads the higher selectivity and higher etch rate of Si1-xGex films to Si films due to the increase in the potential differences of SRP and Si1-xGex valence band edge. For the case of a conventional wet etchant using peracetic acid (PAA) or hydrogen peroxide (H2O2) as an oxidant, their SRP are ~1.75 and ~0.69 eV, respectively. However, its selectivity and etch rate of Si1-xGex films to Si films are insufficient at low Ge concentration of Si1-xGex despite the high SRP value of PAA and H2O2 because the bandgap energy of Si1-xGex increase with decreasing Ge concentration.In our research, therefore, we suggested a novel oxidant, sodium periodate (NaIO4) to enhance the etch rate and the selectivity of wet etchant based on the concept of radical generation. We investigated the dependencies of Si-, Si0.7Ge0.3-film etch rate and selectivity on oxidant species, and dependencies of lateral etch rate of Si0.7Ge0.3/Si multi-stack structures on oxidant species. This was motivated by that NaIO4 generates radicals in acidic medium, such as iodyl (IO3 •) and reactive oxygen species (i.e., the superoxide radical (O2 •–) and hydroxyl (•OH) radical), as shown in Fig. 1. SRP of NaIO4 itself has relatively low (~1.60 eV) compared to PAA (~1.75 eV), IO3 •, O2 •– and •OH radicals generated from NaIO4 have higher SRP (O2 •–: ~2.80 eV and •OH: ~2.42 eV), which resulted in a higher etch rate at lower Ge concentration less than 30%.For the experiments, the Si0.7Ge0.3 layer grown on Si and 3-layer Si0.7Ge0.3/Si multi-stack wafers were grown by using ultra-high-vacuum chemical vapor deposition (EUREKA, JUSUNG ENGINEERING). Coupon wafers with 1.5 × 1.5 cm2 of Si0.7Ge0.3 and Si substrate (reference group), and patterned wafers of 3-layer Si0.7Ge0.3/Si multi-stack layers with a line width of 10 μm were prepared and then all samples were dipped in the etchant solutions for 1 min at room temperature. The thickness of the samples was characterized by using spectroscopic ellipsometry (V-VASE, J.A. Woollam). In addition, after etching of the 3-layer Si0.7Ge0.3/Si multi-stack structures, a lateral etch rate were characterized by using field-emissive scanning electron microscope (Helios 5 CX, Thermofisher).It was confirmed that our novel etchant using NaIO4 as an oxidant demonstrated extremely high etch rate for Si0.7Ge0.3 film (140 nm/min), whereas conventional etchant using oxidant PAA and H2O2 demonstrated the etch rate of 5.7 and 2.4 nm/min respectively. In addition, the selectivity between the Si0.7Ge0.3- and Si films etched by using the NaIO4 oxidant was much higher (318:1) than that etched by PAA and H2O2 oxidant (29:1 and 6:1), as shown in Fig. 2, which sufficiently satisfied the requirement of etch rate (>30nm/min) and selectivity (300:1) for fabricating GAAFETs. The lateral etch rate of 3-layer Si0.7Ge0.3/Si multi-stack, mechanism on radical generation of NaIO4, and the characterization method to quantify radicals will be presented in detail. Acknowledgement This work was supported by the Technology Innovation Program (20022467, Development of Wet Etchant and Core Materials for Next Generation Semiconductor Manufacturing Process below 10 nm) funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea) Figure 1

CMOS-Compatible Titanium-Based Micro Supercapacitor With Outstanding Capacitance and Frequency Performances

Micro supercapacitors (MSCs) with high capacitance density offer enormous potential for on-chip energy storage and power supply filtering. However, the capacitance decay under an AC condition and incompatibility with Complementary Metal Oxide Semiconductor Transistor (CMOS) processes greatly restrict their application as filtering capacitors in integrated circuits. This work presents a wafer-level MSC with outstanding capacitance and frequency performances, contributed by the hybrid TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Ti electrode structure and a novel CMOS-compatible fabrication methodology. The highly conductive Ti framework with optimal porous structure provides a fast transfer channel for electrons/ions, while a 6 nm-thick TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , in situ oxidized-grown on the Ti framework, offers exceptional pseudocapacitance. Meanwhile, a 3D electrode architecture is fabricated through a proposed High-Aspect-Ratio Porous Electrode Lift-off (HPEL) process, benefiting capacitance and rate performance. Hence, the MSC shows a capacitance density of 10.12 mF/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at a high scan rate of 1 V/s with a characteristic frequency of 550 Hz, which is superior to the reported on-chip MSCs. Furthermore, such proposed design and fabrication strategies are simple, low-cost, and CMOS-compatible, promising for mass production.

Progress on Memristor-Based Analog Logic Operation

There is always a need for low-power, area-efficient VLSI (Very Large-Scale Integration) design and this need is increasing day by day. However, conventional design methods based on Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) devices and Complementary Metal-Oxide-Semiconductor Transistor (CMOS) technology cannot meet the performance requirements. The memristor, as a promising computing and memory integration device, offers a new research idea for conventional logic circuit structure and architecture innovation, given its non-volatility, scalability, low power consumption, fast switching speed, etc. This paper proposes a brief overview of the characteristics and current status of memristor-based logic circuits and analyzes their applications in numerical expression and memory. The benefits and drawbacks of various analog logic circuit structures are summarized and compared. In addition, some solution strategies for these issues are presented. Finally, this paper offers prospects for the applications of memristors in the logic implementation of large-scale memristor arrays, the novel structure of in-memory computing, and neural network computing.

A CNTFET Based Bit-Line Powered Stable SRAM Design for Low Power Applications

Higher charge mobility, gate control, and better electrostatics are the key reasons that make carbon nanotube field effect transistor (CNTFET) a better candidate to become the successor of conventional CMOS transistors. However, the increased charge mobility also enhances the leakage power. This work uses CNTFET for designing a low-power eight-transistor static random access memory (8T SRAM) cell. The leakage power of the proposed cell is reduced by 2.21×compared to conventional 6T SRAM at 0.3V with similar CNTFET parameters. The read and write power delay product of the proposed design is improved by 1.02×and 1.85×, respectively. Moreover, the read/ write/ hold static noise margin of the proposed cell is also enhanced by 1.98×/ 0.99×/ 1.01×, respectively, compared to the conventional 6T design. The proposed cell is also compared with three already proposed CNTFET based 8T SRAM designs. Cadence Virtuoso simulation tool and Stanford University 32 nm CNTFET verilog-A model file are used to achieve simulation results.

Total ionizing dose radiation hardening technology based on double-charge multiple-step ion implantation

This paper describes the total ionizing dose (TID) radiation hardening of buried oxide in separation by implantation of oxygen silicon on insulator (SOI) substrates. In this study, 0.5-μm partially depleted SOI complementary metal–oxide–semiconductor (CMOS) transistors and circuits were prepared using double-charge multiple-step ion implantation and annealing, and the changes in the drive current, leakage current, and threshold voltage of the CMOS transistor under different TID radiation conditions were compared. Under a TID of 500 k Rad(Si), radiation-hardened H-type N-channel metal–oxide–semiconductor transistors had a threshold voltage drift of <100 mV in the worst case, and H-type P-channel metal–oxide–semiconductor transistors had a threshold voltage drift of <150 mV. Under a TID of 1 Mrad(Si), CMOS transistors showed no significant increase in leakage current caused by TID radiation. Under a TID of 500 k Rad(Si), the standby current of the radiation-hardened 32-bit DSP was <1.5 mA. The high-density integrated circuits prepared using this technology performed well under harsh ionizing radiation environments. Finally, this technology was compared with similar foreign technologies and TID-unhardened wafers with hardened wafers. This technology reached the international advanced level among equivalent technologies regarding hole capture cross section and maximum threshold voltage drift in the model. PACS85.30.De 85.30.-e.

High-Bandwidth, Low-Power CMOS Transistor Based CAB for Field Programmable Analog Array

This article presents an integrated current mode configurable analog block (CAB) system for field-programmable analog array (FPAA). The proposed architecture is based on the complementary metal-oxide semiconductor (CMOS) transistor level design where MOSFET transistors operating in the saturation region are adopted. The proposed CAB architecture is designed to implement six of the widely used current mode operations in analog processing systems: addition, subtraction, integration, multiplication, division, and pass operation. The functionality of the proposed CAB is demonstrated through these six operations, where each operation is chosen based on the user’s selection in the CAB interface system. The architecture of the CAB system proposes an optimized way of designing and integrating only three functional cells with the interface circuitry to achieve the six operations. Furthermore, optimized programming and digital tuning circuitry are implemented in the architecture to control and interface with the functional cells. Moreover, these designed programming and tuning circuitries play an essential role in optimizing the performance of the proposed design. Simulation of the proposed CMOS Transistor Based CAB system is carried out using Tanner EDA Tools in 0.35 μm standard CMOS technology. The design uses a V power supply and results in maximum 3 dB bandwidth of 34.9 MHz and an approximate size of 0.0537 . This demonstrates the advantages of the design over the current state-of-the-art designs presented for comparison in this article. Consequently, the proposed design has a clear aspect of simplicity, low power consumption, and high bandwidth operation, which makes it a suitable candidate for mobile telecommunications applications.

Ring Oscillator for 60 Meter Bandwidth

The 60-meter band range is tremendously useful in telecommunication, military and governmental applications. The I. T. U. (International Telecommunication Union) required isolationism to former radio frequency services because the various frequency bands are extremely overloaded. The allocation of new frequency bands are a lengthy procedure as well as time taking. As a result, the researchers use bidirectional, amateur radio frequency communication for 60-meter band, usually the frequency slot of 5250–5450 KHz, although the entire band is not essentially obtainable for all countries. For transmission and reception of these frequencies, a local oscillator is used in the mixer unit to generate the local signal for mixing the input and reference signals. For this function different type of oscillators are used. In this paper, a three-stage ring oscillator is designed with 1 V supply. Ring oscillators (RO) is the base to explore like to identifying, specify with modelling resources in the disparity in behaviour of the circuit in terms of industrialized design and layout parameters. This type of oscillators are free from noise as inductor is not used to the circuit as in LC oscillator, Heartly oscillator, Colpitt and tuned oscillators. The present approach of circuit designing, the scaling of CMOS (Complementary Metal Oxide Semiconductor) transistor will moderate, the procedure variability. In the forthcoming article, a ring oscillator with fixed capacitor (1 pF) and with variable capacitors (1 to 100 pF) is analysed. The frequency analysis with different capacitor is performed. The total delay of 3-stage oscillator is 4.82 ns with 5.2 MHz oscillation frequency. The overall Power dissipation of the circuit is 1.852 μW at 1 V supply. The simulation analysis is performed on 45 nm CMOS technology with both transistor width are 278 and 420 nm.

Performance Analysis and Comparison of Different High-K Materials Used as Gate Dielectrics in DH-TMSG MOSFET

Abstract: To overcome SCEs and provide better packing density and performance a device called Double Halo Triple Material Surround Gate MOSFET is introduced. The device is designed by the combination of gate engineering and channel engineering. The device uses a surround gate MOSFET with triple material gate employing gate material engineering which improves the gate transport efficiency by modifying electric field pattern and surface potential along channel, resulting in higher carrier transport efficiency and SCEs. To extend the use of CMOS technology beyond 14 nm node technology, new device materials are required that can enhance the performance of MOSFETs. The use of high-k materials in double gate (DG) MOSFET can triumph over the problem of power dissipation and leakage current. The further mitigation in device dimension becomes a challenging task due to the existence of unavoidable short channel effects. The introduction of gate stack and channel engineering in MOSFET devices open a new window for future generation devices. The gate dielectric materials have played a significant role in the design of novel and high performances at nanoscale of electrical devices. It can be observed that when approaching a higher value of dielectric constant, the on current increases while the subthreshold slope (SS) threshold voltage (Vth) and leakaga current reduced. The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin that the gate leakage current becomes too large.

Demonstration of Multiply-Accumulate Operation With 28 nm FeFET Crossbar Array

This letter reports a linear multiply-accumulate (MAC) operation conducted on a crossbar memory array based on 28nm high-k metal gate (HKMG) Complementary Metal Oxide Semiconductor (CMOS) and ferroelectric field effect transistor (FeFET). The fabrication is conducted at GlobalFoundries with their standard 28nm technology. The crossbar arrays show a 100% yield in MAC operation on a 300mm wafer. The arrays were divided into <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${8}\times {8}$ </tex-math></inline-formula> segments. The FeFET crossbar arrays were fabricated with access transistors, current-limiter transistors and a current-mode analog-to-digital converter (ADC) on the same wafer. Finally, the data retention characteristics reveal excellent data retention characteristics up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${5}\times {10} ^{{4}}$ </tex-math></inline-formula> seconds, which makes this memory array suitable for carrying out MAC operations in inference engine applications.

Complementary Transistors Based on Aligned Semiconducting Carbon Nanotube Arrays.

High-density semiconducting aligned carbon nanotube (A-CNT) arrays have been demonstrated with wafer-scale preparation of materials and have shown high performance in P-type field-effect transistors (FETs) and great potential for applications in future digital integrated circuits (ICs). However, high-performance N-type FETs (N-FETs) have not yet been implemented with A-CNTs, making development of complementary metal-oxide-semiconductor (CMOS) technology, a necessary component for modern digital ICs, impossible. In this work, we reveal the mechanism hindering the realization of A-CNT N-FETs contacted by low-work-function metals and develop corresponding solutions to promote the performance of N-FETs to that of P-type FETs (P-FETs). The fabricated scandium (Sc)-contacted A-CNT N-FET with a 100 nm gate length exhibits an on-state current (Ion) of 800 μA/μm and a peak transconductance (gm) of 250 μS/μm, representing the highest performance of CNT-based N-FETs to date. Moreover, CMOS technology has been developed to realize N- and P-FETs with symmetric high performance based on A-CNTs. The fabricated A-CNT CMOS FETs show electron and hole mobilities of 325 and 241 cm2 V-1 s-1, respectively, which are slightly higher than the corresponding values of Si CMOS transistors. Our scalable fabrication of A-CNT CMOS FETs with comparable electronic performance to Si CMOS will promote the application of CNT-based electronics in digital ICs.

Design of joint reconfigurable hybrid adder and subtractor using FinFET and GnrFET technologies

Many applications, such as integrated circuit based digital signal processors (DSPs) and arithmetic logical units (ALUs), rely on adders and subtractors, which are fundamental blocks. Traditional adders and subtractors were created using complementary metal oxide semi-conductor (CMOS) and field effect transistor (FET) technologies, which have increased the number of transistors, path delays, and power consumption. Therefore, this article focuses on the implementation of hybrid adders and subtractors utilizing FinFET and graphene nano-ribbon FET (GnrFET) based nanotechnologies. Initially, a multiplexer logic-based carry output predictable full adder (COPFA) is developed with a fast selection of carry-outputs, which significantly reduces the delays generated in sum estimation. Then, a path selectable reconfigurable hybrid adder (PSRHA) is developed by selecting the high-speed and low-speed carry propagation paths through the COPFA module. Further, a path selectable reconfigurable hybrid subtractor (PSRHS) also developed using two-complement PSRHA addition. Finally, a single architecture for both addition and subtraction are achieved through a joint reconfigurable hybrid adder and subtractor (JRHAS). From the simulations, the COPFA module resulted in a propagation delay (PD) of 7.2792 ns, static power consumption (SPC) of 2.4369nw, and total energy consumption (TEC) of 0.9077 nJ, while the PSRHA module resulted in PD of 2.45317 ns, SPC of 2.55681nw, TEC of 0.0912 nJ. In addition, the PSRHS module resulted in PD as 2.5297 ns, SPC as 2.8428nw, TEC as 0.0662 nJ, and the JRHAS module resulted in PD as 17.178 ns, SPC as 5.4036nw, TEC as 2.0543 nJ. Overall simulations revealed that the proposed COPFA, PSRHA, PSRHS, and JRHAS resulted in optimal performance as compared to conventional methods in terms of power, delay, and energy metrics.

CMOS Transistors Based First-Order Voltage-Mode All-Pass Filter with Tunable Transformation Possibility

In this paper, a novel complementary metal-oxide semiconductor (CMOS) transistors based first-order voltage-mode all-pass filter is proposed. The filter circuit employs six metal-oxide semiconductor (MOS) transistors and minimal number of passive components, i.e., a resistor and a capacitor. The core of the proposed filter is a CMOS inverting amplifier with unity gain. The proposed circuit exhibits some attractive features such as compact design, high input impedance and ability to provide non-inverting and inverting all-pass responses simultaneously. Additionally, it does not require any kind of passive element matching constraints. Furthermore, by replacing the passive resistor with an active negative channel metal-oxide semiconductor (NMOS) transistor, the proposed filter is enriched with the much-desired feature of tunability. The theoretical behavior is tested and demonstrated by carrying SPICE simulations using TSMC 0.18[Formula: see text][Formula: see text]m level-7 CMOS process parameters.

A Design of Real-Time Data Acquisition and Processing System for Nanosecond Ultraviolet-Visible Absorption Spectrum Detection

Ultraviolet-visible absorption spectroscopy is widely used to monitor water quality, and rapid optical signal detection is a key technology in the process of spectrum measurement. In this paper, an ultrafast spectrophotometer system that can achieve spectrum data acquisition in a single flash of the xenon lamp (within 200 ns) is introduced, and a real-time denoising method for the spectrum is implemented on a field programmable gate array (FPGA) to work cooperatively with the nanosecond spectrum acquisition system, in order to guarantee the quality of the spectrum signals without losing running speed. The hardware of the data acquisition and processing system are constructed on a Xilinx Spartan 6 FPGA chip and its peripheral circuit, including an analog to digital converter and a complementary metal-oxide-semiconductor transistor (CMOS) sensor’s diver circuit. An oversampling method that is suitable for the CMOS sensor’s output is proposed, which works on the CMOS sensor’s dark current noise and readout noise. Another moving-average filter method is designed adaptively, which works on the low-frequency component to filter out the residual spectrum noise of the spectrum signal. The implementation of the filter on the FPGA has been optimized by using a pipelined structure and dual high-speed random-access memory (RAM). As a result, the CMOS linear image sensor successfully captured the spectrum of xenon flash light at the readout clock frequency of 500 kHz and the processing manipulation to the full UV-Vis spectrum data was accomplished at a sub-microsecond speed performance. After the digital filter and oversampling technology were implemented, the coefficient of variation of the measurements reduced from 9.57% to 1.74%, while the signal noise ratio (SNR) of the absorption spectrum increased nine times, compared to the raw data of the CMOS sensor’s output. The tests towards different analyte samples were conducted, and the system shows good performance on distinguishing different concentrations of different analyte solutions on both ultra-violet and visible spectrum bands. The present work showcases the potential of the CMOS sensor’s technique for the fast detection of contaminated water containing nitrate and organic compounds.

Programmable Universal Filter and Quadrature Oscillator Using Single Output Operational Transconductance Amplifiers

This paper presents a new programmable universal filter and quadrature oscillator based on single output operational transconductance amplifiers (OTAs). The proposed universal filter and quadrature oscillator can be achieved into single topology by programming using analog switches. When the circuit programs as a universal filter, it can realize low-pass, high-pass, band-pass, band-stop and all-pass filters with orthogonal and electronic controls of the natural frequency and the quality factor. When the circuit programs as a quadrature oscillator, it provides three-phase quadrature output signals which the condition of oscillation and the frequency of oscillation can be controlled orthogonally and electronically. The proposed structure can be realized based on single output OTAs which is easily implemented both commercially available integrated circuits as OTAs and complementary metal-oxide semiconductor and bipolar junction transistor OTA as IC forms. The performance of the proposed circuit is investigated by SPICE simulation using standard 0.18 μm CMOS process and experiment test using LM13600 discrete component integrated circuit as OTAs is used to confirm the workability of the new circuit.