Complementary Metal Oxide Semiconductor Technology Research Articles

In situ grazing incidence synchrotron x-ray diffraction studies on the wakeup effect in ferroelectric Hf0.5Zr0.5O2 thin films

The discovery of ferroelectricity in HfO2 ultrathin films has gathered considerable interest from the microelectronic industry owing to their compatibility with complementary metal oxide semiconductor technology. However, a significant challenge in utilizing HfO2 thin films for commercial devices is the wakeup effect, which is an increase in polarization with the number of electric field cycles in HfO2-based capacitors. Despite efforts to develop wakeup-free HfO2 thin films, the root cause of this effect remains elusive. Some studies attribute it to the tetragonal (T) to orthorhombic (O) phase transformation, while others suggest it is due to the redistribution of oxygen vacancies within the HfO2 layer during electric field cycling. This study investigated the phase transformation dynamics and oxygen vacancy distributions in TiN/Hf0.5Zr0.5O2/TiN capacitors subjected to electric field cycling using in situ grazing incidence synchrotron x-ray diffraction and ex situ x-ray photoelectron spectroscopy. The as-grown HZO films were crystallized in a mixed phase consisting of monoclinic (M), tetragonal, and orthorhombic fractions. The T-phase volume fraction decreased continuously up to 10k electric field cycles. In contrast, the O-phase fraction increased within the first 100 cycles and then stabilized with further cycling. The redistribution of oxygen vacancies occurred continuously throughout the cycling process. The results revealed that continuous oxygen vacancy redistribution during electric field cycling resulted in phase transformation between the T-, O-, and M-phases. The study provides insight into the phase transformation dynamics and oxygen vacancy redistribution in TiN/Hf0.5Zr0.5O2/TiN capacitors during electric field cycling, shedding light on the underlying mechanisms of the wakeup effect.

Design and Implementation of a 2-input Arithmetic and Logic Unit using Quantum-dot Cellular Automata

Quantum-Dot-Cellular Automata (QCA), an emerging nanotechnology rooted in Coulomb repulsion, holds the ability to supplant orthodox complementary metal-oxide semiconductor (CMOS) technology. Its distinctive advantages lie in ultra-low power consumption, fast switching speed, and high-density structures. This study conducts an extensive literature review to introduce an Arithmetic and Logic Unit (ALU) based on QCA principles. The proposed QCA-based ALU incorporates fundamental logic gates, adders, and subtractors, leveraging the latest XOR gate. Utilizing simulation via QCA Designer 2.0.3, an in-depth performance evaluation of the model is conducted, comparing it with established ALUs based on metrics encompassing cell count, delay, and area. The findings showcase the efficiency of the proposed ALU, characterized by its minimal requirement of 277 cells, an area occupancy of 0.43 µm², and a delay of 2.75 clock cycles. This outcome highlights the favorable attributes of our design compared to existing alternatives, suggesting its potential contribution to the advancement of QCA-based digital circuitry. DUJASE Vol. 8 (1) 26-31, 2023 (January)

Hybrid Quantum-Dot Cellular Automata Nanocomputing Circuits

Quantum-dot cellular automata (QCA) is an emerging transistor-less field-coupled nanocomputing (FCN) approach to ultra-scale ‘nanochip’ integration. In QCA, to represent digital circuitry, electrostatic repulsion between electrons and the mechanism of electron tunnelling in quantum dots are used. QCA technology can surpass conventional complementary metal oxide semiconductor (CMOS) technology in terms of clock speed, reduced occupied chip area, and energy efficiency. To develop QCA circuits, irreversible majority gates are typically used as the primary components. Recently, some studies have introduced reversible design techniques, using reversible majority gates as the main building block, to develop ultra-energy-efficient QCA circuits. However, this approach resulted in time delays, an increase in the number of QCA cells used, and an increase in the chip area occupied. This work introduces a novel hybrid design strategy employing irreversible, reversible, and partially reversible QCA gates to establish an optimal balance between power consumption, delay time, and occupied area. This hybrid technique allows the designer to have more control over the circuit characteristics to meet different system needs. A combination of reversible, irreversible, and innovative partially reversible majority gates is used in the proposed hybrid design method. We evaluated the hybrid design method by examining the half-adder circuit as a case study. We developed four hybrid QCA half-adder circuits, each of which simultaneously incorporates various types of majority gates. The QCADesigner-E 2.2 simulation tool was used to simulate the performance and energy efficiency of the half-adders. This tool provides numerical results for the circuit input/output response and heat dissipation at the physical level within a microscopic quantum mechanical model.

Noise coupling reduction using temperature enhanced device for future integrated circuit integration applications

<p>Information technology-to-internet of things may have succeeded because of fast silicon chip capability expansion. Moore's law, which reduces device size, boosted integrated circuit (IC) performance. Delay rises with highdensity connection parasitic capacitance. Interconnect delays have surpassed transistor delays and slowed progress. An alternative is required now to reduce connection latency. The third dimension is used in popular 3D IC technology IC technology requires through silicon via (TSV) for signal integrity and heat mitigation. Noise coupling hinders electrical communication between signal-carrying TSVs (aggressive TSVs) and ground TSVs (victim TSVs), a 3D IC bottleneck. TSVs must be dielectrically insulated from Si substrates to avoid electrical signal interference. Additionally, first-order modelling will confirm the suggestions. This article proposes using the nanosheet field effect transistor (NSFET) to overcome 3D IC noise coupling and complementary metal oxide semiconductor (CMOS) technology nodes. After discussing the electronic industry and sub nm, several basic metrics and criteria for developing electronic components are presented. The first technique uses Perylene-N's exceptional noise-cancelling characteristics. Second technique uses electrical TSV (ETSV), thermal TSV (TTSV), and heat source models to measure noise coupling on numerous ICs. The third proposes many noise-reducing materials. The suggested structures outperform traditional approaches.</p>

Quad-functioning parity layout for nanocomputing: A QCA design

Quantum dot cellular automata (QCA) is considered an alternative to conventional technologies like CMOS (Complementary Metal-Oxide-Semiconductor) technology due to its potential for lower power consumption, higher speed, and increased device density. QCA introduces a novel approach to designing nano communication circuits and systems. Nano communications data mistakes are detected via parity generators and checkers. The parity bit of each data block ensures that the number of 1′s is either even or odd. Consequently, the system requires four circuits: an even parity generator, an odd parity generator, an even parity checker, and an odd parity checker. The whole system requires more space and cell complexity. In this work, we propose a QCA architecture that serves as a generator for both even and odd parities, as well as a checker for both even and odd parities. It is a quad-functioning circuit that performs four distinct operations within a single design, utilizing 118 QCA cells and occupying an area of 0.17 μm2. The recommended approach uses an efficient XOR gate, resulting in improvements across several performance metrics. QCAPro calculates energy dissipation and design parameters. The recommended QCA circuit outperformed similar QCA circuits in size, complexity, and energy dissipation. The circuit's design cost functions are also low. There has been a 17% reduction in latency and an 86% improvement in QCA-specific costs when compared to the optimal existing design. Moreover, it necessitates a 40% reduction in majority gate usage. The proposed design may compete effectively with other equivalent higher-order circuit designs by reducing the need for multiple blocks in conventional circuits to execute the same task. This architecture holds potential benefits for nano processors and nano communication networks.

Effects of Fe Contamination on the Reliability of Gate Oxide Integrity in Advanced CMOS Technology

Fe contamination has always been one of the most critical issues in the integrated circuit (IC) industry due to its catastrophic effect on device reliability and electrical characteristics. With complementary metal oxide semiconductor (CMOS) technology scaling down, this issue has been attracting more attention. In this paper, the impact of Fe impurity on the reliability of gate oxide integrity (GOI) in advanced CMOS technology is investigated. Intentional contamination of polysilicon gates was conducted in both boron- and phosphorus-doped devices. Failure analysis of the gate oxide was conducted with high-resolution transmission electron microscopy (HRTEM) and the energy dispersive X-ray (EDX) technique. The experimental results disclose that the properties of PMOS are much more sensitive to Fe contamination than those of NMOS. It is suggested that the reason for the above phenomena is that Fe precipitates at the PMOS gate/oxide interface but dissolves uniformly in the NMOS poly gate due to lower formation energy of the FeB pair (0.65 eV) in PMOS than that of the P4-Fe cluster (3.2 eV) in NMOS.

Low‐temperature chemical vapor deposition growth of 2D materials

AbstractTwo‐dimensional (2D) materials have atomic thickness, and thickness‐dependent electronic transport, optical and thermal properties, highlighting great promise applications in future semiconductor devices. Chemical vapor deposition (CVD) is considered as an industry‐oriented method for macro‐synthesis of 2D materials. In conventional CVD, high temperatures are required for the synthesis of high‐quality large‐size 2D materials, which is incompatible with of back‐end‐of‐line of the complementary metal oxide semiconductor (CMOS) techniques. Therefore, low‐temperature synthesis of 2D materials is of critical importance for the advancement toward practical applications of 2D materials with the CMOS technologies. In this review, we focus on strategies for the low‐temperature growth of 2D materials, including the use of low‐melting‐point precursors, metal‐organic CVD, plasma‐enhanced CVD, van der Waals‐substrate vapor phase epitaxy, tellurium‐assisted CVD, salt‐assisted CVD, etc., with discussions of their reaction mechanisms, applications, associated advantages, and limitations. We also provide an outlook and perspectives of future low‐temperature chemical vapor deposition growth of 2D materials.

Design of a high-speed MCML D-Latch at 0.6 V in 45 nm CMOS technology

Metal oxide semiconductor (MOS) current mode logic (MCML) is generally preferred for high-speed circuit design. In this paper, a novel low voltage folded (LVF) MCML D-Latch is designed. The existing topologies of the MCML D-Latch consume more power and operate at 1 V. The proposed D-Latch can operate at 0.6V with better delay and power management. MCML circuits minimize delay and perform fast operations, hence it can be used in high-frequency applications. The proposed LVF MCML D–Latch is analyzed with the parameters such as power, delay, power delay product and output noise using cadence virtuoso in 45 nm complementary metal oxide semiconductor (CMOS) technology at a voltage of 0.6 V and a temperature of 27 °C. The proposed technique achieves 62.11% of power reduction, transient response speed improved by 51.23% and noise cancellation becomes 26.13% improvement over the existing circuit. It also achieves 96% of output swing which is more efficient compared to others. Finally, the parametric analysis is performed with different temperatures to verify the stability of the proposed circuit. From the simulated results, it is clear that the proposed LVF MCML D-Latch provides better performance in high-speed phase locked loop (PLL) applications.

A Li-ion battery charger based on LDO regulator with pre-charge mode in 180 nm CMOS technology

This paper presents a novel Li-Ion battery charger that utilizes a low-dropout (LDO) regulator and incorporates four control modes: low constant current mode, pre-charge current mode, fast constant current mode, and constant voltage mode. The charger aims to meet specific criteria such as high precision, high efficiency, and small form factor. Through simulation results, the following specifications were obtained using a 1.8 V supply in a 0.18 μm complementary metal–oxide–semiconductor (CMOS) technology: a trickle current of 124.7 mA, a pre-charge current of 466.94 mA, a maximum charge current of 1.06 A, and a charge voltage of 4.21 V. The proposed charger demonstrates an efficiency of 92%.

A method to design a fast chaotic oscillator using CCTA

This article introduces a novel method for designing a fast chaotic oscillator using a CCTA (Current Conveyor Transconductance Amplifier) based on Chua's circuit. The proposed method uses innovative configurations and advanced simulation techniques to overcome challenges in high-speed operation, nonlinear dynamics, and Analog Building Block (ABB) selection. The design begins with nonlinear negative resistance, essential for Chua's diode characteristics, including two negative resistances, NR1 and NR2. The circuit integrates one CCTA block, two grounded capacitors, two fixed resistors, one inductor, and one potentiometer. It is simulated using PSPICE with IC (Integrated Circuit) macro-models and 180nm CMOS (Complementary Metal Oxide Semiconductor) technology. Various chaotic waveforms and attractors are produced, validating the theoretical and mathematical predictions. By varying the resistance values (1450Ω, 1650Ω, 1800Ω, 1950Ω), the circuit exhibits different chaotic behaviors, such as large limit cycles, double-scroll attractors, Rossler-type attractors, and I-periodic attractors. FFT (Fast Fourier Transform) analysis confirms the highest dominant operating frequency of 37.5MHz. A Monte Carlo simulation with 100 runs shows maximum voltage variations in the chaotic waveforms of 5.21 % and 4.61 % across the capacitors, demonstrating robustness and reliability. This design offers significant advancements in implementing high-frequency chaotic oscillators, with potential applications in various fields requiring chaotic signal generation.•A novel design of Chua's diode and Chua's chaotic oscillator using only one CCTA block is presented in this paper.•The proposed chaotic oscillator achieves the highest operating frequency of 37.5MHz.•The proposed circuit is simulated using commercially available ICs (MAX435 and AD844) and CMOS 180nm technology in PSPICE to confirm its workability.

Advancements in CMOS image sensors for enhanced vehicle assistance technologies

The burgeoning adoption of new energy vehicles has precipitated a surge in advanced vehicular assistant technologies, encompassing systems such as assisted driving and parking. The efficacy of these technologies hinges critically on the selection of suitable image sensors, which are integral to fulfilling the stringent image quality requisites necessary for the implementation of these technologies. Predominantly, these assistant systems are reliant on sophisticated image processing techniques, necessitating high-quality images as a fundamental input for efficacious analysis and recognition. Currently, the Complementary Metal-Oxide-Semiconductor (CMOS) image sensor is predominantly employed in vehicular systems, a choice underpinned by its advantageous attributes such as resistance to interference, cost-effectiveness, and high degree of integration. This paper aims to elucidate the developmental trajectory and fundamental principles of CMOS technology and its application in image sensors. It delves into an analysis of the salient features of CMOS image sensors, especially in their application to parking assistance, autonomous driving support, and fatigue detection systems. Conclusively, the paper offers an exhaustive overview of the current state of CMOS image sensor development, alongside a projection of future trends and an exploration of the challenges that must be surmounted to advance this field further.

Design and Analysis of Low-Power and Area-Efficient Master-Slave Flip-Flop

In this paper, a novel master-slave flip-flop is designed that incorporates 15 transistors and a single-phase clock, employing topological and adaptive coupling methods. The proposed flip-flop circuit (PFC) is more efficient than other logic-structured flip-flops. PFC is designed using a 45 nm Complementary Metal Oxide Semiconductor (CMOS) technology node. Notably, the PFC exhibits an impressive 34.18%, 42.92%, 39.71%, 44.39%, and 46.91% improvement in average power consumption compared to the adaptive data track flip-flop (ADTFF), Hybrid Flip-Flop (HFF),18-transistor single-phase clocked (18TSPC), Logic Structured Reduction Flip-Flop (LSRFF), and Topologically compressed flip-flop (TCFF). It also improved the C to Q delay, power delay product (PDP). Monte Carlo simulations of average power and C to Q delay have been performed for 1000 samples. By reducing the number of PMOS transistors, the total area of the PFC is minimized. PFC operates effectively within a clock frequency range of up to 1 GHz.

Fundamental 1:2 demultiplexer design in quantum-dot cellular automata nanotechnology

There are many issues with complementary metal oxide semiconductor (CMOS) technology in the ultra-nanoscale regime. A quantum-dot cellular automaton (QCA) is a promising innovation for crafting logic circuits in nanoscale dimensions. It provides lower power dissipation, better functionality, faster switching frequency, and better performance than that of the CMOS technology, which makes it a potential candidate for succeeding the CMOS technology. Demultiplexer is a needed operation to operate at the receiver side of the communication system, which converts the multiplexed data into original ones. Hence, a fundamental 1:2 demultiplexer is proposed using QCA technology. The proposed demultiplexer uses only 17 QCA cells and a single clock. The proposed 1:2 demultiplexer decreases the number of cells, hence occupying less layout area and a minimum clock as compared to the available works in the field. The proposed demultiplexer circuit improves the cell count by 19.05 %, the QCA clock by 50 % and the QCA cost by 64.25 % as compared to the best reported work in the literature. The energy dissipation of the suggested demultiplexer is examined using the QCA Designer-E and QCA Pro-tools. The proposed demultiplexer dissipates only 1.38 meV of average energy per cycle and is computed using the QCA Designer-E tool. The total energy dissipation for the proposed demultiplexer is improved by 22.85 % as compared to the best-reported work in the literature and is estimated using the QCA Pro-tool.

First Demonstration of High‐Frequency InAlN/GaN High‐Electron‐Mobility Transistor Using GaN‐on‐Insulator Technology via 200 mm Wafer Bonding

In0.17Al0.83N/GaN high‐electron‐mobility transistor (HEMT) using GaN‐on‐Insulator (GaNOI) technology via 200 mm wafer bonding technique is developed with good DC and RF performance and high fT/fmax. Measurements obtained from X‐Ray diffraction and micro‐Raman spectroscopy have demonstrated a 5% reduction in “a lattice strain,” which results in the improvement of the sheet resistance (Rsh) from 301 to 284 Ω □−1. A 120 nm gate‐length device achieves a peak fT up to 96 GHz which yields a fT × Lg value of 11.5 GHz μm, which compares favorably with reported GaN‐based HEMTs on Si. These results demonstrate that GaNOI HEMT on Si is an attractive candidate for future mm‐wave applications. The implementation of GaNOI technology facilitates the integration of GaN devices into a chip alongside complementary metal–oxide–semiconductor technology that opens up the potential for integrated high‐power and RF applications, enabling more compact and efficient systems.

A low power 10‐bit 1 MS/s cyclic analog to digital converter for complementary metal oxide semiconductors image sensors with comparator‐based switched‐capacitor technique

AbstractThis paper proposes a power‐optimized column‐parallel cyclic analog to digital converter (ADC) for complementary metal oxide semiconductors (CMOS) image sensor readout circuits. The design combines a 2.5‐bit/cycle architecture with a comparator shutdown technique based on the comparator‐based switched‐capacitor (CBSC) circuits, which results in a significant reduction in the operating time of the threshold detection comparator compared with conventional CBSC circuits. This reduction in operating time leads to power savings as the threshold detection comparator can be shut down quickly. The paper also presents a comprehensive analysis of the nonideal factors of CBSC circuits and the coarse and fine conversion allocation scheme. The 10‐bit two‐stage comparator‐based cyclic ADC is designed in a 110 nm 1P4 M CMOS technology. Simulation results show that the effective number of bit (ENOB) is 9.7 bits, with each column consuming 103 W of power. The proposed cyclic ADC has a figure of merit (FOM) of 123 fJ/conv‐step. Compared with conventional structures, the proposed design reduces the power consumption of the ADC by 34.3% while maintaining the same level of performance.

Elucidating the formation mechanisms of the parasitic channel with buffer-free GaN/Si hetero-bonding structures

Driven by the increasing demand for 5G communication, GaN radio frequency (RF) device on Si technology has been flourishing attributable to the large size, low cost, and compatibility with complementary metal–oxide–semiconductor technology. However, a significant challenge is that a high-conductance parasitic channel forms at the interface between the III-N epitaxial layers and the Si substrate, leading to severe RF loss, which has been considerably impairing both the performance and advancement of RF GaN-on-Si technologies. Despite continuing controversies concerning the physical mechanisms engendering the parasitic channel, clarification is critically needed. Standing apart from traditional studies on RF loss in III-N epilayers grown on Si, this article comprehensively investigates the bonding interface of GaN thin film and Si(100) substrate realized via direct surface activated bonding and ion-cutting technologies. It was clearly determined that substantial diffusion of gallium (Ga) atoms into the Si substrate at the bonding interface occurred even at an annealing temperature as low as 350 °C. Subsequent high-temperature post-annealing at 800 °C intensified this diffusion, activating Ga atoms to form a p-type highly conductive parasitic channel. Simultaneously, it triggered Ga atoms aggregation and incited melt-back etching within the Si substrate at the interface. Contrasting with the conventional hetero-epitaxy, this study presents a compelling view based on the bonding technique. It conclusively elucidates the physical mechanisms of the formation of the primary source of RF loss—the p-type highly conductive parasitic channel.

Analysis of P-N Junction Length of Drain and Source in MOSFET Transistor Through TCAD Simulation

This paper delves into the convergence of mathematical and computer science principles within the realm of electronics engineering, particularly focusing on device-level transistor restructuring. A pressing challenge confronting the semiconductor sector is the persistent escalation of leakage current alongside technological advancements. At the heart of any chip or semiconductor device lies the transistor, serving as its fundamental building block. Among the various forms of leakage current, subthreshold leakage stands out as a dominant component in transistors. Within this study, a systematic exploration of the numerical association governing the physical configuration of MOSFET and leakage amount specifically the subthreshold one is undertaken. One innovative algorithm is crafted to facilitate the automated tracking of transistor structures, laying the groundwork for subsequent analyses. The simulation framework is meticulously constructed by leveraging mathematical formulations derived from the algorithmic outputs. Remarkably, the results obtained from the simulation conducted through TCAD software exhibit a remarkable proximity to established mathematical models. Given the ubiquity of Complementary Metal Oxide Semiconductor (CMOS) technology in contemporary semiconductor fabrication, it serves as the cornerstone for the simulation endeavours herein.

Reconfigurable Low-Power CMOS Amplifier Stages for Broadband Impedance Spectroscopy

In this paper, a fully differential amplifier is proposed in a 1.8 V-0.18 μm CMOS (Complementary Metal-Oxide-Semiconductor) technology, which can accommodate both voltage (V-mode) and current (C-mode) inputs. Post-layout simulation results show a fixed gain amplifier exhibiting a 26 dB (V-mode)/89 dBΩ (C-mode) gain and a programmable gain amplifier featuring a 6–26 dB gain, overall yielding a 26.8–46.4 dB dB (V-mode)/89.6–109.2 dBΩ (C-mode) programmable gain range, with a 100 MHz bandwidth and a power and area consumption of 360.5 µW and 0.0177 mm2, respectively. This amplifier has been designed considering the constraints and specifications (including low voltage, low power, reduced noise and high common mode rejection ratio) for its use in an analogue Lock-in-based Frequency Response Analyser-Impedance Spectroscopy (FRA-IS) device. The proposed design introduces a novel fully differential open-loop structure based on a transconductance–transimpedance (TC-TI) topology for high performance applications with a broad programmable bandwidth. To compare this work, different figures of merit (FoMs) are introduced as well as a comparison table with other simulated and experimental results, reporting an overall better performance in terms of gain, frequency and power-area consumption.

Multi-project wafers for flexible thin-film electronics by independent foundries

Flexible and large-area electronics rely on thin-film transistors (TFTs) to make displays1–3, large-area image sensors4–6, microprocessors7–11, wearable healthcare patches12–15, digital microfluidics16,17 and more. Although silicon-based complementary metal–oxide–semiconductor (CMOS) chips are manufactured using several dies on a single wafer and the multi-project wafer concept enables the aggregation of various CMOS chip designs within the same die, TFT fabrication is currently lacking a fully verified, universal design approach. This increases the cost and complexity of manufacturing TFT-based flexible electronics, slowing down their integration into more mature applications and limiting the design complexity achievable by foundries. Here we show a stable and high-yield TFT platform for the fabless manufacturing of two mainstream TFT technologies, wafer-based amorphous indium–gallium–zinc oxide and panel-based low-temperature polycrystalline silicon, two key TFT technologies applicable to flexible substrates. We have designed the iconic 6502 microprocessor in both technologies as a use case to demonstrate and expand the multi-project wafer approach. Enabling the foundry model for TFTs, as an analogy of silicon CMOS technologies, can accelerate the growth and development of applications and technologies based on these devices.

Calculating and analyzing time delay in zigzag graphene nanoscrolls based complementary metal-oxide-semiconductors

Graphene Nano Scrolls (GNSs) and Zigzag graphene nanoscrolls (ZGNSs) are semi-one-dimensional materials with exceptional electrical and optical properties, making them attractive to be used in nanoelectronics and complementary metal–oxide–semiconductor (CMOS) technology. With in CMOS device technology, time delay is a crucial issue in the design and implementation of CMOS based ZGNSs. Current paper focus is on ZGNSs application in the channel area of metal–oxide–semiconductor field-effect transistors (MOSFETs) in CMOS technology. We studied analytically, the importance of different parameters on time delay reduction, resulting in faster switching and higher frequency in integrated circuits (ICs). The results of this research demonstrates that, the ZGNS-based CMOS proves considerable variations in the current due to the geometrical parameters, such as chirality number, channel length, and nanoscroll length which can be engineered to produce faster ICs.