Complementary Metal Oxide Semiconductor Technology Research Articles

Noise coupling reduction using temperature enhanced device for future integrated circuit integration applications

<p>Information technology-to-internet of things may have succeeded because of fast silicon chip capability expansion. Moore's law, which reduces device size, boosted integrated circuit (IC) performance. Delay rises with highdensity connection parasitic capacitance. Interconnect delays have surpassed transistor delays and slowed progress. An alternative is required now to reduce connection latency. The third dimension is used in popular 3D IC technology IC technology requires through silicon via (TSV) for signal integrity and heat mitigation. Noise coupling hinders electrical communication between signal-carrying TSVs (aggressive TSVs) and ground TSVs (victim TSVs), a 3D IC bottleneck. TSVs must be dielectrically insulated from Si substrates to avoid electrical signal interference. Additionally, first-order modelling will confirm the suggestions. This article proposes using the nanosheet field effect transistor (NSFET) to overcome 3D IC noise coupling and complementary metal oxide semiconductor (CMOS) technology nodes. After discussing the electronic industry and sub nm, several basic metrics and criteria for developing electronic components are presented. The first technique uses Perylene-N's exceptional noise-cancelling characteristics. Second technique uses electrical TSV (ETSV), thermal TSV (TTSV), and heat source models to measure noise coupling on numerous ICs. The third proposes many noise-reducing materials. The suggested structures outperform traditional approaches.</p>

Design of a high-speed MCML D-Latch at 0.6 V in 45 nm CMOS technology

Metal oxide semiconductor (MOS) current mode logic (MCML) is generally preferred for high-speed circuit design. In this paper, a novel low voltage folded (LVF) MCML D-Latch is designed. The existing topologies of the MCML D-Latch consume more power and operate at 1 V. The proposed D-Latch can operate at 0.6V with better delay and power management. MCML circuits minimize delay and perform fast operations, hence it can be used in high-frequency applications. The proposed LVF MCML D–Latch is analyzed with the parameters such as power, delay, power delay product and output noise using cadence virtuoso in 45 nm complementary metal oxide semiconductor (CMOS) technology at a voltage of 0.6 V and a temperature of 27 °C. The proposed technique achieves 62.11% of power reduction, transient response speed improved by 51.23% and noise cancellation becomes 26.13% improvement over the existing circuit. It also achieves 96% of output swing which is more efficient compared to others. Finally, the parametric analysis is performed with different temperatures to verify the stability of the proposed circuit. From the simulated results, it is clear that the proposed LVF MCML D-Latch provides better performance in high-speed phase locked loop (PLL) applications.

A Li-ion battery charger based on LDO regulator with pre-charge mode in 180 nm CMOS technology

This paper presents a novel Li-Ion battery charger that utilizes a low-dropout (LDO) regulator and incorporates four control modes: low constant current mode, pre-charge current mode, fast constant current mode, and constant voltage mode. The charger aims to meet specific criteria such as high precision, high efficiency, and small form factor. Through simulation results, the following specifications were obtained using a 1.8 V supply in a 0.18 μm complementary metal–oxide–semiconductor (CMOS) technology: a trickle current of 124.7 mA, a pre-charge current of 466.94 mA, a maximum charge current of 1.06 A, and a charge voltage of 4.21 V. The proposed charger demonstrates an efficiency of 92%.

Design and Analysis of Low-Power and Area-Efficient Master-Slave Flip-Flop

In this paper, a novel master-slave flip-flop is designed that incorporates 15 transistors and a single-phase clock, employing topological and adaptive coupling methods. The proposed flip-flop circuit (PFC) is more efficient than other logic-structured flip-flops. PFC is designed using a 45 nm Complementary Metal Oxide Semiconductor (CMOS) technology node. Notably, the PFC exhibits an impressive 34.18%, 42.92%, 39.71%, 44.39%, and 46.91% improvement in average power consumption compared to the adaptive data track flip-flop (ADTFF), Hybrid Flip-Flop (HFF),18-transistor single-phase clocked (18TSPC), Logic Structured Reduction Flip-Flop (LSRFF), and Topologically compressed flip-flop (TCFF). It also improved the C to Q delay, power delay product (PDP). Monte Carlo simulations of average power and C to Q delay have been performed for 1000 samples. By reducing the number of PMOS transistors, the total area of the PFC is minimized. PFC operates effectively within a clock frequency range of up to 1 GHz.

Fundamental 1:2 demultiplexer design in quantum-dot cellular automata nanotechnology

There are many issues with complementary metal oxide semiconductor (CMOS) technology in the ultra-nanoscale regime. A quantum-dot cellular automaton (QCA) is a promising innovation for crafting logic circuits in nanoscale dimensions. It provides lower power dissipation, better functionality, faster switching frequency, and better performance than that of the CMOS technology, which makes it a potential candidate for succeeding the CMOS technology. Demultiplexer is a needed operation to operate at the receiver side of the communication system, which converts the multiplexed data into original ones. Hence, a fundamental 1:2 demultiplexer is proposed using QCA technology. The proposed demultiplexer uses only 17 QCA cells and a single clock. The proposed 1:2 demultiplexer decreases the number of cells, hence occupying less layout area and a minimum clock as compared to the available works in the field. The proposed demultiplexer circuit improves the cell count by 19.05 %, the QCA clock by 50 % and the QCA cost by 64.25 % as compared to the best reported work in the literature. The energy dissipation of the suggested demultiplexer is examined using the QCA Designer-E and QCA Pro-tools. The proposed demultiplexer dissipates only 1.38 meV of average energy per cycle and is computed using the QCA Designer-E tool. The total energy dissipation for the proposed demultiplexer is improved by 22.85 % as compared to the best-reported work in the literature and is estimated using the QCA Pro-tool.

First Demonstration of High‐Frequency InAlN/GaN High‐Electron‐Mobility Transistor Using GaN‐on‐Insulator Technology via 200 mm Wafer Bonding

In0.17Al0.83N/GaN high‐electron‐mobility transistor (HEMT) using GaN‐on‐Insulator (GaNOI) technology via 200 mm wafer bonding technique is developed with good DC and RF performance and high fT/fmax. Measurements obtained from X‐Ray diffraction and micro‐Raman spectroscopy have demonstrated a 5% reduction in “a lattice strain,” which results in the improvement of the sheet resistance (Rsh) from 301 to 284 Ω □−1. A 120 nm gate‐length device achieves a peak fT up to 96 GHz which yields a fT × Lg value of 11.5 GHz μm, which compares favorably with reported GaN‐based HEMTs on Si. These results demonstrate that GaNOI HEMT on Si is an attractive candidate for future mm‐wave applications. The implementation of GaNOI technology facilitates the integration of GaN devices into a chip alongside complementary metal–oxide–semiconductor technology that opens up the potential for integrated high‐power and RF applications, enabling more compact and efficient systems.

A low power 10‐bit 1 MS/s cyclic analog to digital converter for complementary metal oxide semiconductors image sensors with comparator‐based switched‐capacitor technique

AbstractThis paper proposes a power‐optimized column‐parallel cyclic analog to digital converter (ADC) for complementary metal oxide semiconductors (CMOS) image sensor readout circuits. The design combines a 2.5‐bit/cycle architecture with a comparator shutdown technique based on the comparator‐based switched‐capacitor (CBSC) circuits, which results in a significant reduction in the operating time of the threshold detection comparator compared with conventional CBSC circuits. This reduction in operating time leads to power savings as the threshold detection comparator can be shut down quickly. The paper also presents a comprehensive analysis of the nonideal factors of CBSC circuits and the coarse and fine conversion allocation scheme. The 10‐bit two‐stage comparator‐based cyclic ADC is designed in a 110 nm 1P4 M CMOS technology. Simulation results show that the effective number of bit (ENOB) is 9.7 bits, with each column consuming 103 W of power. The proposed cyclic ADC has a figure of merit (FOM) of 123 fJ/conv‐step. Compared with conventional structures, the proposed design reduces the power consumption of the ADC by 34.3% while maintaining the same level of performance.

Elucidating the formation mechanisms of the parasitic channel with buffer-free GaN/Si hetero-bonding structures

Driven by the increasing demand for 5G communication, GaN radio frequency (RF) device on Si technology has been flourishing attributable to the large size, low cost, and compatibility with complementary metal–oxide–semiconductor technology. However, a significant challenge is that a high-conductance parasitic channel forms at the interface between the III-N epitaxial layers and the Si substrate, leading to severe RF loss, which has been considerably impairing both the performance and advancement of RF GaN-on-Si technologies. Despite continuing controversies concerning the physical mechanisms engendering the parasitic channel, clarification is critically needed. Standing apart from traditional studies on RF loss in III-N epilayers grown on Si, this article comprehensively investigates the bonding interface of GaN thin film and Si(100) substrate realized via direct surface activated bonding and ion-cutting technologies. It was clearly determined that substantial diffusion of gallium (Ga) atoms into the Si substrate at the bonding interface occurred even at an annealing temperature as low as 350 °C. Subsequent high-temperature post-annealing at 800 °C intensified this diffusion, activating Ga atoms to form a p-type highly conductive parasitic channel. Simultaneously, it triggered Ga atoms aggregation and incited melt-back etching within the Si substrate at the interface. Contrasting with the conventional hetero-epitaxy, this study presents a compelling view based on the bonding technique. It conclusively elucidates the physical mechanisms of the formation of the primary source of RF loss—the p-type highly conductive parasitic channel.

Analysis of P-N Junction Length of Drain and Source in MOSFET Transistor Through TCAD Simulation

This paper delves into the convergence of mathematical and computer science principles within the realm of electronics engineering, particularly focusing on device-level transistor restructuring. A pressing challenge confronting the semiconductor sector is the persistent escalation of leakage current alongside technological advancements. At the heart of any chip or semiconductor device lies the transistor, serving as its fundamental building block. Among the various forms of leakage current, subthreshold leakage stands out as a dominant component in transistors. Within this study, a systematic exploration of the numerical association governing the physical configuration of MOSFET and leakage amount specifically the subthreshold one is undertaken. One innovative algorithm is crafted to facilitate the automated tracking of transistor structures, laying the groundwork for subsequent analyses. The simulation framework is meticulously constructed by leveraging mathematical formulations derived from the algorithmic outputs. Remarkably, the results obtained from the simulation conducted through TCAD software exhibit a remarkable proximity to established mathematical models. Given the ubiquity of Complementary Metal Oxide Semiconductor (CMOS) technology in contemporary semiconductor fabrication, it serves as the cornerstone for the simulation endeavours herein.

Reconfigurable Low-Power CMOS Amplifier Stages for Broadband Impedance Spectroscopy

In this paper, a fully differential amplifier is proposed in a 1.8 V-0.18 μm CMOS (Complementary Metal-Oxide-Semiconductor) technology, which can accommodate both voltage (V-mode) and current (C-mode) inputs. Post-layout simulation results show a fixed gain amplifier exhibiting a 26 dB (V-mode)/89 dBΩ (C-mode) gain and a programmable gain amplifier featuring a 6–26 dB gain, overall yielding a 26.8–46.4 dB dB (V-mode)/89.6–109.2 dBΩ (C-mode) programmable gain range, with a 100 MHz bandwidth and a power and area consumption of 360.5 µW and 0.0177 mm2, respectively. This amplifier has been designed considering the constraints and specifications (including low voltage, low power, reduced noise and high common mode rejection ratio) for its use in an analogue Lock-in-based Frequency Response Analyser-Impedance Spectroscopy (FRA-IS) device. The proposed design introduces a novel fully differential open-loop structure based on a transconductance–transimpedance (TC-TI) topology for high performance applications with a broad programmable bandwidth. To compare this work, different figures of merit (FoMs) are introduced as well as a comparison table with other simulated and experimental results, reporting an overall better performance in terms of gain, frequency and power-area consumption.

Multi-project wafers for flexible thin-film electronics by independent foundries

Flexible and large-area electronics rely on thin-film transistors (TFTs) to make displays1–3, large-area image sensors4–6, microprocessors7–11, wearable healthcare patches12–15, digital microfluidics16,17 and more. Although silicon-based complementary metal–oxide–semiconductor (CMOS) chips are manufactured using several dies on a single wafer and the multi-project wafer concept enables the aggregation of various CMOS chip designs within the same die, TFT fabrication is currently lacking a fully verified, universal design approach. This increases the cost and complexity of manufacturing TFT-based flexible electronics, slowing down their integration into more mature applications and limiting the design complexity achievable by foundries. Here we show a stable and high-yield TFT platform for the fabless manufacturing of two mainstream TFT technologies, wafer-based amorphous indium–gallium–zinc oxide and panel-based low-temperature polycrystalline silicon, two key TFT technologies applicable to flexible substrates. We have designed the iconic 6502 microprocessor in both technologies as a use case to demonstrate and expand the multi-project wafer approach. Enabling the foundry model for TFTs, as an analogy of silicon CMOS technologies, can accelerate the growth and development of applications and technologies based on these devices.

Calculating and analyzing time delay in zigzag graphene nanoscrolls based complementary metal-oxide-semiconductors

Graphene Nano Scrolls (GNSs) and Zigzag graphene nanoscrolls (ZGNSs) are semi-one-dimensional materials with exceptional electrical and optical properties, making them attractive to be used in nanoelectronics and complementary metal–oxide–semiconductor (CMOS) technology. With in CMOS device technology, time delay is a crucial issue in the design and implementation of CMOS based ZGNSs. Current paper focus is on ZGNSs application in the channel area of metal–oxide–semiconductor field-effect transistors (MOSFETs) in CMOS technology. We studied analytically, the importance of different parameters on time delay reduction, resulting in faster switching and higher frequency in integrated circuits (ICs). The results of this research demonstrates that, the ZGNS-based CMOS proves considerable variations in the current due to the geometrical parameters, such as chirality number, channel length, and nanoscroll length which can be engineered to produce faster ICs.

Multi-laser source interference suppression using the time-coding method for SPAD-based flash DToF systems

Flash-type direct time-of-flight (DToF) image sensors use an in-pixel successive approximation register time-to-digital converter (SAR TDC) for time quantization. However, in a scene where multiple DToF systems exist simultaneously, different laser signals from multiple sources will produce mutual signal interference between DToF systems, causing the DToF system’s incorrect measurement. In this paper, we present a method called time coding, which inserts delay time bins between different working periods to suppress the interference laser together with the SAR TDC. The time-coding method is designed using a 110 nm complementary metal oxide semiconductor (CMOS) technology and verified by behavioral model and circuit simulation. Regardless of traditional systems or systems equipped with time coding, DToF systems with certain patterns of time coding can reduce interference noise by at least 95%, maintaining a measurement accuracy of 99% or higher at long distances.

A review of silicon carbide CMOS technology for harsh environments

A comprehensive overview of the advancements, challenges, and prospects of silicon carbide (SiC) complementary metal-oxide-semiconductor (CMOS) technology is presented. As the demand for high-performance and energy-efficient electronic devices continues to grow, SiC has emerged as a promising material due to its unique properties. The paper aims to provide a thorough understanding of the state-of-the-art developments in SiC CMOS technology. The paper delves into the key features of SiC and its compatibility with CMOS processing techniques. It highlights the challenges associated with SiC CMOS technology, such as substrate quality, interface states, and process integration. Examples of CMOS circuitry that have been successfully designed, fabricated, and tested are provided.

Physical implementation of cobalt ferrite memristor in Chua's circuit for chaotic encryption

Memory resistor, or memristor, has been realized as a discrete electronic device and has a perspective application in the field of cryptography. The physical implementation of the memristor in chaotic circuits has been scarcely explored. In this paper, a memristor is fabricated by spin-coating a cobalt ferrite precursor on a processed silicon and is then electro-sputtered with silver to act as the anode with the base silicon as the cathode. This fabrication process has a scalability potential in conjunction with integrated circuit fabrication techniques and complementary metal oxide semiconductor (CMOS) technologies. The fabricated cobalt ferrite memristor has shown a ratio between the on and off resistance of >1000 and has been implemented in a chaotic Chua's circuit, making it one of few physical implementations of a physical memristor in a physical circuit. The analysis and characterization of this circuit using bifurcation diagrams and Lyapunov exponent prove the chaotic behavior of a real Chua's circuit. This chaotic behavior can be useful in chaotic cryptography as nonperiodic oscillations can be leveraged to make sensitive information more difficult to interpret by bad actors.

Analysis Of P-N Junction Length of Drain and Source in MOSFET Transistor Through TCAD Simulation

This paper delves into the convergence of mathematical and computer science principles within the realm of electronics engineering, particularly focusing on device-level transistor restructuring. A pressing challenge confronting the semiconductor sector is the persistent escalation of leakage current alongside technological advancements. At the heart of any chip or semiconductor device lies the transistor, serving as its fundamental building block. Among the various forms of leakage current, subthreshold leakage stands out as a dominant component in transistors. Within this study, a systematic exploration of the numerical association governing the physical configuration of MOSFET and leakage amount specifically the subthreshold one is undertaken. One innovative algorithm is crafted to facilitate the automated tracking of transistor structures, laying the groundwork for subsequent analyses. The simulation framework is meticulously constructed by leveraging mathematical formulations derived from the algorithmic outputs. Remarkably, the results obtained from the simulation conducted through TCAD software exhibit a remarkable proximity to established mathematical models. Given the ubiquity of Complementary Metal Oxide Semiconductor (CMOS) technology in contemporary semiconductor fabrication, it serves as the cornerstone for the simulation endeavours herein.

An analog to digital converter in a SiC CMOS technology for high-temperature applications

Integrated circuits based on wide bandgap semiconductors are considered an attractive option for meeting the demand for high-temperature electronics. Here, we report an analog-to-digital converter fabricated in a silicon carbide complementary metal–oxide–semiconductor technology now available through Europractice. The MOSFET component in this technology was measured up to 500 °C, and the key parameters, such as threshold voltage, field-effect mobility, and channel-length modulation parameters, were extracted. A 4-bit flash data converter, consisting of 266 transistors, is implemented with this technology and demonstrates correct operation up to 400 °C. Finally, the gate oxide quality is investigated by time-dependent dielectric breakdown measurements at 500 °C. A field-acceleration factor of 4.4 dec/(MV/cm) is obtained by applying the E model.

Design and Simulation of VCO for RF Transceivers with Low Power, Low Phase Noise and Wider Tuning Range using Silterra 130nm CMOS Technology

The performance of low-power transceivers is required to meet stringent specifications for an advanced wireless radio frequency (RF) application. The design topology in this paper is simulated to meet the specifications and operation of VCO for low power, low phase noise and wide tuning range in complementary metal oxide semiconductor (CMOS) 130nm technology for RF transceivers. The relationship between the phase noise, power consumption and frequency turning range is fully analyzed to further improve the performance of the voltage-controlled oscillator (VCO). The architecture of the VCO employs two sets of symmetrical cross-couple split NMOS and PMOS with biased current sources operating in the triode region, and a resonator tank that achieves the desired low phase noise performance of about -110 dB/Hz at a tuning range of 4.1 to 4.5 GHz with a supply of 0.9 V. The control of the DC bias point reduces the conduction angle, which improves the current efficiency, power consumption and phase noise. The topology generates sufficient –gm for the oscillator incorporation to mitigate the start-up issue of the VCO. At the center frequency of 4.38 GHz, the VCO serves as a promising solution for improving low power and low phase for wireless communication systems and RF transceiver applications. The design consumes a very low power of 0.138 mW, achieves a phase noise of -110.53 dBc/Hz at 1 MHz offset, and a figure of merit (FoM) of -191.90 dBc/Hz.

A Novel Approach for Realizing Loop-Filter in Low-Distortion Noise-Coupled ΣΔ Modulators

This paper presents an innovative general structure for a single-loop Sigma-Delta ([Formula: see text]) modulator that combines low-distortion and noise-coupled techniques to achieve high-resolution for low-power applications. The low-distortion technique adjusts the signal transfer function of the proposed structure to unity, while the noise-coupled technique enhances the order of quantization noise-shaping at the modulator output. These techniques were incorporated into the design to increase the modulator order without requiring additional operational amplifiers during its circuit implementation, resulting in a low-power modulator compared to similar structures. To reduce the number of required amplifiers, a second-order infinite impulse response (IIR) filter was used in the modulator loop filter, in place of two integrators. To assess the proposed structure’s performance, a third-order modulator sample was implemented and simulated for speech recognition applications, specifically, digital hearing aids, using 180[Formula: see text]nm complementary metal oxide semiconductor (CMOS) technology. The results indicate that for a third structure with a sampling rate of 64, an input sine signal of −6[Formula: see text]dBFS and a sampling frequency of 2.56[Formula: see text]MHz, the signal to noise plus distortion (SNDR) was 81.9[Formula: see text]dB, and the dynamic range (DR) was 88[Formula: see text]dB for a 20[Formula: see text]KHz bandwidth. The modulator’s power consumption was 126.9[Formula: see text][Formula: see text]W. Circuit and system-level simulations demonstrate the effectiveness of the proposed method.

Selective Growth of GaP Crystals on CMOS-Compatible Si Nanotip Wafers by Gas Source Molecular Beam Epitaxy.

Gallium phosphide (GaP) is a III-V semiconductor with remarkable optoelectronic properties, and it has almost the same lattice constant as silicon (Si). However, to date, the monolithic and large-scale integration of GaP devices with silicon remains challenging. In this study, we present a nanoheteroepitaxy approach using gas-source molecular-beam epitaxy for selective growth of GaP islands on Si nanotips, which were fabricated using complementary metal-oxide semiconductor (CMOS) technology on a 200 mm n-type Si(001) wafer. Our results show that GaP islands with sizes on the order of hundreds of nanometers can be successfully grown on CMOS-compatible wafers. These islands exhibit a zinc-blende phase and possess optoelectronic properties similar to those of a high-quality epitaxial GaP layer. This result marks a notable advancement in the seamless integration of GaP-based devices with high scalability into Si nanotechnology and integrated optoelectronics.