Analysis of P-N Junction Length of Drain and Source in MOSFET Transistor Through TCAD Simulation

Abstract

This paper delves into the convergence of mathematical and computer science principles within the realm of electronics engineering, particularly focusing on device-level transistor restructuring. A pressing challenge confronting the semiconductor sector is the persistent escalation of leakage current alongside technological advancements. At the heart of any chip or semiconductor device lies the transistor, serving as its fundamental building block. Among the various forms of leakage current, subthreshold leakage stands out as a dominant component in transistors. Within this study, a systematic exploration of the numerical association governing the physical configuration of MOSFET and leakage amount specifically the subthreshold one is undertaken. One innovative algorithm is crafted to facilitate the automated tracking of transistor structures, laying the groundwork for subsequent analyses. The simulation framework is meticulously constructed by leveraging mathematical formulations derived from the algorithmic outputs. Remarkably, the results obtained from the simulation conducted through TCAD software exhibit a remarkable proximity to established mathematical models. Given the ubiquity of Complementary Metal Oxide Semiconductor (CMOS) technology in contemporary semiconductor fabrication, it serves as the cornerstone for the simulation endeavours herein.