Complementary Metal Oxide Semiconductor Chip Research Articles

Low Phase Noise and Low Power Consumption VCOs Using CMOS and IPD Technologies

This paper presents two voltage controlled oscillators (VCOs) operating at 5.42 and 5.76 GHz implemented in 0.18-μm complementary metal-oxide semiconductor (CMOS) technology with integrated passive device (IPD) inductors. One IPD inductor was stacked on the top of the active region of the 5.76-GHz VCO chip, whereas the other IPD inductor was placed on the top of the 5.42-GHz VCO CMOS chip but far from the its active region. The high-quality IPD inductors reduce the phase noise of the VCOs. The measurements of the two VCOs indicate the same phase noise of -120 dBc/Hz at 1 MHz offset frequency. These results demonstrate a 6-dB improvement compared to the VCO using an on-chip inductor. This paper also presents the effect of the coupling between the IPD inductor and the active region of the chip on the phase noise performance.

Waveguide biosensor with integrated detector array for tuberculosis testing

A label-free immunoassay using a local evanescent array coupled (LEAC) biosensor is reported. Complementary metal oxide semiconductor chips with integrated photoconductor arrays are used to detect an antibody to a M. tuberculosis protein antigen, HspX. The metrology limits of the LEAC sensor using dc and ac measurement systems correspond to average film thicknesses of 28 and 14 pm, respectively. Limits of detection are 87 and 108 pm, respectively, for mouse immunoglobulin G antibody patterning and antigen detection.

Pyramid Architecture for 3840 X 2160 Quad Full High Definition 30 Frames/s Video Acquisition

Image pipeline processing is crucial to generating high quality images in applications using complementary metaloxide-semiconductor (CMOS)/charge-coupled device sensors. The on-chip line buffer normally dominates the total area and power dissipation due to the needed filter window buffering. As image resolution and filter support increase, the area and power requirement increase accordingly. This paper presents a novel pyramid architecture to efficiently process a system that the image pipeline is between an image sensor and video coding engine. By utilizing the features of the pyramid structure and block-based video/image encoders, the proposed architecture is scalable from low to high image resolution and filter size. The input image is first partitioned into floors of tiles to reduce the frame line buffer. Two computing schemes, immediate result reuse and vertical snack scan, are utilized to reduce the overlapping redundant computations. A 90 nm CMOS chip design with 7 × 5 filter support for 3840 × 2160 quad full high definition video at 30 frames/s is designed to demonstrate the performance of power and area efficiency. Compared with traditional architectures with frame line buffers, the proposed design has shown that the power consumption is reduced by 25% to 108 mW from 145 mW. The chip area is reduced by 65% to 309 K from 888 K logic gates. The external memory bandwidth increases to 8286 Mbit/s from 5972 Mbit/s for YUV4:2:0, from 7963 Mbit/s for YUV4:2:2, and is reduced by 30% from 11944 Mbit/s for YUV4:4:4.

Streak camera in standard (Bi)CMOS (bipolar complementary metal-oxide-semiconductor) technology

The conventional streak camera (CSC) is an optoelectronic instrument that captures the spatial distribution as a function of time of an ultra high-speed luminous phenomenon with picosecond temporal resolution and a typical spatial resolution of several tens of micrometers. This paper presents two tubeless streak camera architectures called MISC (matrix integrated streak camera) and VISC (vector integrated streak camera), which replicate the functionality of a CSC on a single CMOS chip. The MISC structure consists of a lens, which spreads the photon flux on the surface of a specific pixel array-based (Bi)CMOS sensor. The VISC architecture is based on a sensor featuring a single column of photodetectors, where each element is coupled to a front-end and a multi-sampling and storage unit. In this case the optical objective used in front of the sensor focuses the luminous event on the several tens of micrometers wide photosensitive column. For both architectures, the spatial resolution is linked to the size of the photodetector and the temporal resolution is determined by the bandwidths of the photodetectors and the signal conditioning electronics. The capture of a 6 ns full width at half maximum 532 nm laser pulse is reported for two generations of MISC and a first generation of VISC.

Integrated Bio-Imaging Sensor Array with Complementary Metal–Oxide–Semiconductor Cascode Source–Drain Follower

A new bio-imaging sensor with photosystem I (PSI) of Thermosynechococcus elongatus and complementary metal–oxide–semiconductor (CMOS) circuits is demonstrated. Photons are converted into electrons by PSI, and electrons are detected as an electric signal by a CMOS integrated circuit. For a sensor circuit, a 4 ×4 sensor array with a CMOS source–drain follower is designed and fabricated by a standard CMOS process. An extended-gate electrode and an SU-8 passivation layer are formed on a CMOS chip by a post-CMOS process, and PSI is electrostatically fixed on the electrode. A 3×4 image of the pattern of light illuminated on a chip is taken with the sensor array, where four cells are used as reference cells.

Actuation of Magnetic Beads on a Complementary Metal–Oxide–Semiconductor Chip for Biological Applications

Magnetic beads with a diameter of 2.8 µm are actuated on a standard complementary metal–oxide–semiconductor (CMOS) chip. The chip was fabricated using the 180 nm process and has two groups of parallel current paths in the top metal layer and the second top metal layer. These two are placed diagonally to each other. Suspended beads were applied onto the chip and a magnetic field that was induced by patterned currents manipulated beads successfully. To observe an effect induced by a thermal convection flow, several current patterns were tested and the actuation of beads was examined. The result suggests that the beads were mainly driven by the magnetic field and partially affected by a convex flow generated by the current on the paths.

Design of a Tunable All-Digital UWB Pulse Generator CMOS Chip for Wireless Endoscope

A novel tunable all-digital, ultrawideband pulse generator (PG) has been implemented in a standard 0.18-¿ m complementary metal-oxide semiconductor (CMOS) process for implantable medical applications. The chip shows that an ultra-low dynamic energy consumption of 27 pJ per pulse without static current flow at a 200-MHz pulse repetition frequency (PRF) with a 1.8-V power supply and low area of 90 × 50 ¿m(2). The PG generates tunable pulsewidth, amplitude, and transmit (Tx) power by using simple circuitry, through precise timing control of the H-bridge output stage. The all-digital architecture allows easy integration into a standard CMOS process, thus making it the most suitable candidate for in-vivo biotelemetry applications.

CMOS-integrated Sensor chip for in-plane and out-of-plane shear stress

This paper reports on the design and characterization of a novel stress sensor chip in complementary metal oxide semiconductor (CMOS)-technology. The chip is capable of detecting two in-plane shear stress components and for the first time two out-of-plane shear stress components at multiple locations. On an area of 2.5 mm×2 mm, the sensors are integrated with an instrumentation amplifier, an A/D-converter and digital logic for signal processing and data transmission via an I2C-bus. The single sensor elements as separate test structures and the CMOS chip are characterized by the application of individual, homogeneous stress components. In every case, linear responses only of the designated sensors are observed. An encapsulation process with two-component epoxy resin reveals that mainly thermo-mechanical normal stress is generated during cooling-down.

Microfluid Ejection Device Based on Complementary Metal–Oxide–Semiconductor Technology as an Artificial Synapse

A complementary metal–oxide–semiconductor (CMOS)-based multisite microfluid ejection device was fabricated and demonstrated. An array of microreservoir cells integrated with micropumps was fabricated on this device. Microfluid ejection is based on the actuation of a silicone membrane between the microreservoir and the micropump cell. This membrane was actuated by the gas produced during the electrolysis of water. The device was equipped with a CMOS chip as an addressable electrode array for multisite microfluid ejection. The microfluid ejection cell array was configured on the CMOS chip to realize addressable microfluid ejection. We measured the membrane displacement to characterize the performance of the micropump, and successfully demonstrated microfluid ejection. The volume of the ejected microfluid was nearly proportional to injected charge. These results suggest that the proposed microfluid ejection device is a promising platform for artificial synaptic devices for various scientific and clinical applications.

Programmable high voltage CMOS chips for particle-based high-density combinatorial peptide synthesis

We built high voltage complementary metal oxide semiconductor (CMOS) chips that generate electrical fields on their surface, such that electrically charged microparticles (diameter 10–20 μm on average) can be addressed on distinct pixel electrodes according to arbitrary field patterns. Each pixel contains a memory cell in canonical low-voltage CMOS-technology controlling a high voltage (30–100 V) potential area on the top metal layer. Particle transfer with minimal contaminations in less than 10 s for a complete chip was observed for pixels of 100 μm × 100 μm down to 65 μm × 65 μm. This allows a new way to create surface modifications on top of CMOS chips without need for additional masks or stamps. Using suitable particles, a chemically modified chip surface, and compatible chemistry, this method can be utilized for self-aligned high-density biopolymer arrays, e.g., peptide arrays. Transfer of microparticles loaded with amino acids for combinatorial peptide synthesis is demonstrated. Successful synthesis of different peptides (octamers) was proven by immunostaining. Based on results obtained by a chip containing pixel areas of different characteristics, a chip for biological applications with 16,384 pixels (10,000 pixel/cm 2) was built. Good homogeneity of peptide synthesis over the chip area was verified by immunostaining.

Life-Cycle Energy Demand and Global Warming Potential of Computational Logic

Computational logic, in the form of semiconductor chips of the complementary metal oxide semiconductor (CMOS) transistor structure, is used in personal computers, wireless devices, IT network infrastructure, and nearly all modem electronics. This study provides a life-cycle energy analysis for CMOS chips over 7 technology generations with the purpose of comparing energy demand and global warming potential (GWP) impacts of the life-cycle stages, examining trends in these impacts over time and evaluating their sensitivity to data uncertainty and changes in production metrics such as yield. A hybrid life-cycle assessment (LCA) model is used. While life-cycle energy and GWP of emissions have increased on the basis of a wafer or die, these impacts have been reducing per unit of computational power. Sensitivity analysis of the model shows that impacts have the highest relative sensitivity to wafer yield, line yield, and die size and largest absolute sensitivity to the use-phase power demand of the chip.

Real-time, multiplexed electrochemical DNA detection using an active complementary metal-oxide-semiconductor biosensor array with integrated sensor electronics

Optical biosensing based on fluorescence detection has arguably become the standard technique for quantifying extents of hybridization between surface-immobilized probes and fluorophore-labeled analyte targets in DNA microarrays. However, electrochemical detection techniques are emerging which could eliminate the need for physically bulky optical instrumentation, enabling the design of portable devices for point-of-care applications. Unlike fluorescence detection, which can function well using a passive substrate (one without integrated electronics), multiplexed electrochemical detection requires an electronically active substrate to analyze each array site and benefits from the addition of integrated electronic instrumentation to further reduce platform size and eliminate the electromagnetic interference that can result from bringing non-amplified signals off chip. We report on an active electrochemical biosensor array, constructed with a standard complementary metal-oxide-semiconductor (CMOS) technology, to perform quantitative DNA hybridization detection on chip using targets conjugated with ferrocene redox labels. A 4×4 array of gold working electrodes and integrated potentiostat electronics, consisting of control amplifiers and current-input analog-to-digital converters, on a custom-designed 5mm×3mm CMOS chip drive redox reactions using cyclic voltammetry, sense DNA binding, and transmit digital data off chip for analysis. We demonstrate multiplexed and specific detection of DNA targets as well as real-time monitoring of hybridization, a task that is difficult, if not impossible, with traditional fluorescence-based microarrays.

Principal Component Analysis-Based Object Detection/Recognition Chip for Wireless Interconnected Three-Dimensional Integration

To develop image detection/recognition systems for various types of multiobjects that operate in real-time/real-world with small-size hardware and low-power dissipation, three-demensional (3-D) integration of multichips is required. We have designed a complementary metal oxide semiconductor (CMOS) test chip for object detection/recognition utilizing the processing algorithm based on the eigenface method and wireless chip-to-chip interconnections. Furthermore, a 3-D integration system was designed utilizing wireless chip-to-chip interconnections of parallel inductor-coupled local wireless interconnect (LWI) for 5.3 Gbps image data transfer, and antenna-coupled global wireless interconnect (GWI) for 500 Mbps clock and command distribution. With the prospect of realizing enhanced system performance using 0.18 µm CMOS chips, object detection/recognition times of 580 µs for detection and 4.2 µs for one-to-one recognition, and 40 giga operation per second (GOPS) processing capabilities at a 250 MHz clock frequency were obtained.

Precise selective deposition of microparticles on electrodes of microelectronic chips

We examined the high precision deposition of toner and polymer microparticles with a typical size of approximately 10 microm on electrode arrays with electrodes of 100 microm and below using custom-made microelectronic chips. Selective desorption of redundant particles was employed to obtain a given particle pattern from preadsorbed particle layers. Microparticle desorption was regulated by dielectrophoretic attracting forces generated by individual pixel electrodes, tangential detaching forces of an air flow, and adhesion forces on the microchip surface. A theoretical consideration of the acting forces showed that without pixel voltage, the tangential force applied for particle detachment exceeded the particle adhesion force. When the pixel voltage was switched on, however, the sum of attracting forces was larger than the tangential detaching force, which was crucial for desorption efficiency. In our experiments, appropriately large dielectrophoretic forces were achieved by applying high voltages of up to 100 V on the pixel electrodes. In addition, electrode geometries on the chip's surface as well as particle size influenced the desorption quality. We further demonstrated the compatibility of this procedure to complementary metal oxide semiconductor chip technology, which should allow for an easy technical implementation with respect to high-resolution microparticle deposition.

Hybrid carbon nanotube-silicon complementary metal oxide semiconductor circuits

A hybrid technology is presented that combines carbon nanotube field-effect transistors (CNFET) with conventional, silicon-based complementary metal oxide semiconductor (CMOS) technology. The fabrication involves the chemical vapor deposition growth and optical characterization of carbon nanotubes, which are then transferred with lithographic precision onto a commercially fabricated CMOS substrate. In this manner, CNFET devices are fabricated on top of the interconnection network of the CMOS chip, providing a three-dimensional integration of active devices, “sandwiching” wiring, and passives. As a demonstration of this approach, a simple hybrid CNFET/CMOS inverter is fabricated and tested.

Reprogrammable optical phase array

A novel reprogrammable optical phase array (ROPA) device is presented as a reconfigurable electro-optic element. One specific application of the ROPA, a 1 x 6 electro-optic space switch, is fully described. Switching angles are within 2 degrees , and switching is achieved through a complementary metal-oxide semiconductor (CMOS) controlled, diffraction based, optical phase array in a bulk BaTiO3 crystal. The crystal is flip-chipped to the CMOS chip, creating a compact fully integrated device. The design, optical simulation, and fabrication of the device are described, and preliminary experimental results are presented.

Fabrication and performance of microbolometer arrays based on nanostructured vanadiumoxide thin films

In this paper, 32 × 32 infrared (IR) uncooled focal plane arrays (UFPAs) based on nanostructured vanadium oxide(VOx) thermally sensitive material are fabricated by micromachining processes.The thermally sensitive element is fabricated on the complementarymetal–oxide–semiconductor (CMOS) chip after planarization of its surface. In thispaper, silicon dioxide is used as a buffer layer for fabrication of nanostructuredVOx. The interconnection of the CMOS chip and the sensitive array is accomplished byelectroless plating of nickel (Ni) metal, which shows good electrical conductivityperformance. The IR sensitive testing results illustrate that the response of themicrobolometer is obvious and the average responsivity and normalized detectivity are1.26 × 104 V W−1 and 2.04 × 107 cm W−1 Hz1/2, respectively.

Fabrication and Validation of Multichip Neural Stimulator for In vivo Experiments toward Retinal Prosthesis

A complementary metal oxide semiconductor (CMOS) multichip neural stimulator was fabricated and characterized. The device was designed specifically for retinal prosthesis. In this work, to achieve required performances for in vivo experiments, a new CMOS unit chip was designed with a power-on-reset mechanism and a low series resistance. We have developed a fabrication process for the proposed device focusing on the tight-seal performance of the device against saline solution to achieve a reliable long term operation. The proposed packaging technology is based on a flip-chip technique and has a feature of embedded Pt bulk electrodes. The basic functionality of the fabricated CMOS chip and packaged stimulator was confirmed. The device passed a 10-day endurance test in saline solution.

A Custom Chip Set for a Frequency-Agile High-Resolution Sonar Array

This paper describes two custom-integrated circuits, which form the core building blocks of a versatile wideband sonar array. An analog 0.5-mum complementary metal-oxide-semiconductor (CMOS) chip houses a preamplifier, an antialias filter, and a high-resolution (14-16 b) data converter based on delta-sigma modulation techniques. A complementary 0.35-mum digital CMOS chip incorporates a four-stage multirate filter cascade, which provides a wideband and two narrowband outputs. The complex narrowband outputs are obtained via a subsampling mixer and span over the top 15% or the top 10%, respectively, of the original band. The system sampling clock can vary from 2 to 10 MHz to enable tuning to a specific frequency window located anywhere between 30 and 150 kHz. Both chips process four sonar channels in parallel and, when clocked at 10 MHz, dissipate a combined power of 416 mW (104 mW per channel).

Integrated cell manipulation system—CMOS/microfluidic hybrid

Manipulation of biological cells using a CMOS/microfluidic hybrid system is demonstrated. The hybrid system starts with a custom-designed CMOS (complementary metal-oxide semiconductor) chip fabricated in a semiconductor foundry. A microfluidic channel is post-fabricated on top of the CMOS chip to provide biocompatible environments. The motion of individual biological cells that are tagged with magnetic beads is directly controlled by the CMOS chip that generates microscopic magnetic field patterns using an on-chip array of micro-electromagnets. Furthermore, the CMOS chip allows high-speed and programmable reconfiguration of the magnetic fields, substantially increasing the manipulation capability of the hybrid system. Extending from previous work that verified the concept of the hybrid system, this paper reports a set of manipulation experiments with biological cells, which further confirms the advantage of the hybrid approach. To enhance the biocompatibility of the system, the microfluidic channel is redesigned and the temperature of the device is monitored by on-chip sensors. Combining microelectronics and microfluidics, the CMOS/microfluidic hybrid system presents a new model for a cell manipulation platform in biological and biomedical applications.