Complementary Metal Oxide Semiconductor Chip Research Articles

Applications of three-dimensional LSI

Abstract

5-Gb/s and 10-GHz Center-Frequency Gaussian Monocycle Pulse Transmission Using 65-nm Logic CMOS With On-Chip Dipole Antenna and High-<inline-formula> <tex-math notation="TeX">\(\kappa \) </tex-math></inline-formula> Interposer

Interchip data transmission was demonstrated using impulse radio ultrawideband complementary metal- oxide-semiconductor (CMOS) transmitter integrate circuits with on-chip dipole antennas. A differential pseudorandom binary sequence of 2 7 data of Gaussian monocycle pulse (GMP) was formed by 65-nm CMOS logic circuits using upand downpulses with certain gate delays. The CMOS transmitter generated 5-Gb/s GMP with the center frequency of 10 GHz. To improve transmission gains, an interposer with the high dielectric constant (e r = 38) and optimized thickness was inserted under the CMOS chips as a dielectric slab waveguide. 2-Gb/s GMP signals were transmitted and received in the distance of 10 mm by use of the CMOS on-chip antennas and the high-κ interposer.

A hybrid system of carbon ink electrodes and chromatography paper on a CMOS chip and its application to enzymatic glucose sensor

Enzymatic sensors on complementary metal–oxide–semiconductor (CMOS) chips are realized using carbon ink and chromatography paper (ChrPr). Electrodes are fabricated from carbon ink on CMOS chips. The carbon ink electrodes work as well-behaving electrochemical electrodes. Enzyme electrodes are realized by covering the carbon ink electrodes on the CMOS chip with ChrPr supporting enzymes and electron mediators. Such enzyme electrodes successfully give anodic current proportional to the glucose concentration. Good linearity is observed up to 10 mM glucose concentration, which is sufficient for blood glucose testing applications.

Digital control system design and analyses of a 3-phase bearingless induction motor

The overall conguration of a magnetic suspension decoupling control system is designed to realize the reliable digital control of a 3-phase bearingless induction motor whose rotor windings are not pole-specic. Based on a digital signal processor complementary metal-oxide semiconductor chip, the digital control hardware and software systems are analyzed and designed. In this paper, the calculation and regulation of the motor rotational speed, correction and regulation methods of the radial displacements, calculation and compensation algorithms of the unilateral magnetic pulls, induction compensation algorithm of the eective suspension control current, current regulation, and space-vector pulse width modulation algorithms, are presented in detail. The experimental results verify the feasibility and practicability of the designed decoupling digital control system of the 3-phase bearingless induction motor.

2.4-GHz Complementary Metal Oxide Semiconductor Power Amplifier Using High-Quality Factor Wafer-Level Bondwire Spiral Inductor

A complementary metal oxide semiconductor (CMOS) power amplifier (PA) using a wafer-level bondwire spiral inductor with high-quality factor (Q) is presented. The inductor is made by three top metal traces connected with bondwire loops above the CMOS chip. The proposed inductor with 2.75-nH inductance achieves a Q of 18, which is three times as much as that of a conventional CMOS standard spiral inductor at 2.4 GHz. The Q of the inductor is over 15 from 2 to 14 GHz, which can cover the frequency band of wireless sensor network and worldwide interoperability for microwave access applications. The output power and power-added efficiency of the PA with the inductor are improved by 1.5 dBm and 7% as compared with those of the fully integrated CMOS PA, respectively.

A CMOS magnetic microbead-based capacitive biosensor array with on-chip electromagnetic manipulation

Magnetic microbeads are widely used in biotechnology and biomedical research for manipulation and detection of cells and biomolecules. Most lab-on-chip systems capable of performing manipulation and detection require external instruments to perform one of the functions, leading to increased size and cost. This work aims at developing an integrated platform to perform these two functions by implementing electromagnetic microcoils and capacitive biosensors on a CMOS (complementary metal oxide semiconductor) chip. Compared to most magnetic-type sensors, our detection method requires no externally applied magnetic fields and the associated fabrication is less complicated. In our experiment, microbeads coated with streptavidin were driven to the sensors in the center of microcoils with functionalized anti-streptavidin antibody. Detection of a single microbead was successfully demonstrated using a capacitance-to-frequency readout. The average capacitance changes for the experimental and control groups were −5.3fF and −0.2fF, respectively.

SWNT Based Nanosensors for Wireless Detection of Explosives and Chemical Warfare Agents

The detection of concealed explosives and chemical warfare agents is an urgent need to protect the safety of people and cities around the world. This requires the development of highly sensitive, portable, and stand-off sensors. Here, we present a wireless sensing unit based on single-walled carbon nanotubes (SWNTs) integrated with complementary metal oxide semiconductor (CMOS) circuitry, which can effectively detect trace explosives and chemical agents. The response of SWNT sensors to Dinitrotoluene (DNT) (a byproduct of TNT) and Dimethyl methylphosphonate (DMMP) (an analog of nerve agent sarin) vapors is improved dramatically after decoration with single stranded-DNA (ss-DNA). The response of carbon nanotube sensors to DNT and DMMP vapors is reversible and repeatable. The nanosensors integrated on a CMOS chip are tested with DMMP (DNT) vapors with concentrations varying from 1.57 to 130.49 ppm (9.41-45.73 ppm), and the corresponding change in resistance of the SWNT sensor varied from 7.5% to 27.5% (6.53-22.76%). The detected signal is processed by off-chip components on a circuitry board and is transmitted wirelessly to a computer. This versatile sensing system provides a promising platform to detect explosives and chemical agents at a trace level in a wireless manner and stand-off distance.

Progress in Ion Torrent semiconductor chip based sequencing

In order for next-generation sequencing to become widely used as a diagnostic in the healthcare industry, sequencing instrumentation will need to be mass produced with a high degree of quality and economy. One way to achieve this is to recast DNA sequencing in a format that fully leverages the manufacturing base created for computer chips, complementary metal-oxide semiconductor chip fabrication, which is the current pinnacle of large scale, high quality, low-cost manufacturing of high technology. To achieve this, ideally the entire sensory apparatus of the sequencer would be embodied in a standard semiconductor chip, manufactured in the same fab facilities used for logic and memory chips. Recently, such a sequencing chip, and the associated sequencing platform, has been developed and commercialized by Ion Torrent, a division of Life Technologies, Inc. Here we provide an overview of this semiconductor chip based sequencing technology, and summarize the progress made since its commercial introduction. We described in detail the progress in chip scaling, sequencing throughput, read length, and accuracy. We also summarize the enhancements in the associated platform, including sample preparation, data processing, and engagement of the broader development community through open source and crowdsourcing initiatives.

Integration of Magnetoresistive Biochips on a CMOS Circuit

Since 2006, fully scalable matrix-based magnetoresistive biochips have been proposed. This integration was initially achieved with thin film switching devices and moved to complementary metal-oxide-semiconductor (CMOS) switching devices and electronics. In this paper, a new microfabrication process is proposed to integrate magnetoresistive sensors on a small CMOS chip (4 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ). This chip includes a current generator, multiplexers, and a diode in series with a spin valve as matrix element. In this configuration, it is shown that the fabricated spin-valves have similar magnetic characteristics when compared to standalone spin valves. This validates the successfulness of the developed microfabrication process. The noise of each matrix element is further characterized and compared to the noise of a standalone spin valve and a portable electronic platform designed to perform biological assays. Although the noise is still higher, the spin valve integrated on the CMOS chip enables an increase in density and compactness of the measuring electronics.

A LabVIEW based automatic test system for sieving chips

The present trend for Complementary Metal Oxide Semiconductor (CMOS) chip designs is smaller in size and power consumption with multifunction. This results the difficulty for the testing engineer, especially for small amount production without an automatic probe station, to complete such task. In order to reduce the workload of the engineer, improve the testing efficiency and accuracy, a LabVIEW based automatic test system for such CMOS chip has been designed in this paper. The details of the overall system which includes the setup of the testing by using a PXI (PCI extensions for instrumentation) system with Data Acquisition (DAQ) and Source Measure Units (SMUs) module, and the LabVIEW based automatic testing program has been introduced in this paper. The testing results have shown that this system is able to improve the testing efficiency with great accuracy, at the same time to evaluate the testing results in real-time. Due to the software is built on different modules, and it is therefore easy to be extended for different applications.

Manipulation of Dispersed Magnetic Beads for On-Chip Immunoassay

To provide a simple and low-cost mobile immunoassay platform, a test chip on which dispersed magnetic beads are manipulated was designed and fabricated by a 180 nm standard complementary metal–oxide–semiconductor (CMOS) process. In preliminary experiments, beads that have a diameter of 2.8 µm were successfully manipulated and their motion were captured and analyzed. Then, an immunoassay was conducted on the chip. First, the nonspecific binding of hydrophilic beads coated with an antibody was compared with that of hydrophobic beads that were used for the preliminary experiments. Next, comparison of an immunoassay of mouse IgG with a control assay and a test on the feasibility of the blocking process were conducted simultaneously. The beads coated with the antibody were successfully immobilized onto the chip surface in the presence of the target antigen, which was checked through bead manipulation. This indicates that an immunoassay on an inexpensive CMOS chip is feasible using an affordable amount of driving current.

Manipulation of Dispersed Magnetic Beads for On-Chip Immunoassay

To provide a simple and low-cost mobile immunoassay platform, a test chip on which dispersed magnetic beads are manipulated was designed and fabricated by a 180 nm standard complementary metal–oxide–semiconductor (CMOS) process. In preliminary experiments, beads that have a diameter of 2.8 µm were successfully manipulated and their motion were captured and analyzed. Then, an immunoassay was conducted on the chip. First, the nonspecific binding of hydrophilic beads coated with an antibody was compared with that of hydrophobic beads that were used for the preliminary experiments. Next, comparison of an immunoassay of mouse IgG with a control assay and a test on the feasibility of the blocking process were conducted simultaneously. The beads coated with the antibody were successfully immobilized onto the chip surface in the presence of the target antigen, which was checked through bead manipulation. This indicates that an immunoassay on an inexpensive CMOS chip is feasible using an affordable amount of driving current.

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Microdisplay technologies for near-to-eye applications mostly use a complementary metal-oxide semiconductor (CMOS) processing chip as backplane for pixel addressing, with extensive post-processing on top of the CMOS chip to deposit organic LED or liquid crystal layers. Here, we examine the possibility of integrating emissive microdisplays within the CMOS chip, with absolutely no post processing needed. This will dramatically reduce the manufacturing cost of microdisplays and may lead to new microdisplay applications. Visible electroluminescence is achieved by biasing pn junctions into avalanche breakdown mode. The most appropriate CMOS pn junction is selected and innovative tech- niques are applied to increase the light extraction efficiency from the CMOS chip using the metal layers of the CMOS process. An 8 × 64 dot matrix microdisplay was designed and manufactured in a 0.35-μm CMOS technology. The experimental results show that a luminance level of 20 cd∕m 2 can be reached, which is an adequate luminance value in order to comfortably read data being displayed in relatively dark environ- ments. The electrical power dissipation per pixel being activated is 0.9 mW∕pixel. It is also shown that the pixels can be switched at a rate faster than 350 MHz. © 2012 Society of Photo-Optical Instrumentation Engineers (SPIE). (DOI: 10.1117/1.OE.51.1.014003)

Visible-Light Communications Using a CMOS-Controlled Micro-Light- Emitting-Diode Array

We report the high-frequency modulation of individual pixels in 8 × 8 arrays of III-nitride-based micro-pixellated light-emitting diodes, where the pixels within the array range from 14 to 84 μ m in diameter. The peak emission wavelengths of the devices are 370, 405, 450 and 520 nm, respectively. Smaller area micro-LED pixels generally exhibit higher modulation bandwidths than their larger area counterparts, which is attributed to their ability to be driven at higher current densities. The highest optical -3 dB modulation bandwidths from these devices are shown to be in excess of 400 MHz, which, to our knowledge, are the highest bandwidths yet reported for GaN LEDs. These devices are also integrated with a complementary metal-oxide-semiconductor (CMOS) driver array chip, allowing for simple computer control of individual micro-LED pixels. The bandwidth of the integrated micro-LED/CMOS pixels is shown to be up to 185 MHz; data transmission at bit rates up to 512 Mbit/s is demonstrated using on-off keying non return-to-zero modulation with a bit-error ratio of less than 1 × 10-10, using a 450 nm-emitting 24 μm diameter CMOS-controlled micro-LED. As the CMOS chip allows for up to 16 independent data inputs, this device demonstrates the potential for multi-Gigabit/s parallel data transmission using CMOS-controlled micro-LEDs.

Single-cell recording and stimulation with a 16k micro-nail electrode array integrated on a 0.18 μm CMOS chip

To cope with the growing needs in research towards the understanding of cellular function and network dynamics, advanced micro-electrode arrays (MEAs) based on integrated complementary metal oxide semiconductor (CMOS) circuits have been increasingly reported. Although such arrays contain a large number of sensors for recording and/or stimulation, the size of the electrodes on these chips are often larger than a typical mammalian cell. Therefore, true single-cell recording and stimulation remains challenging. Single-cell resolution can be obtained by decreasing the size of the electrodes, which inherently increases the characteristic impedance and noise. Here, we present an array of 16,384 active sensors monolithically integrated on chip, realized in 0.18 μm CMOS technology for recording and stimulation of individual cells. Successful recording of electrical activity of cardiac cells with the chip, validated with intracellular whole-cell patch clamp recordings are presented, illustrating single-cell readout capability. Further, by applying a single-electrode stimulation protocol, we could pace individual cardiac cells, demonstrating single-cell addressability. This novel electrode array could help pave the way towards solving complex interactions of mammalian cellular networks.

Integration of Solar Cells on Top of CMOS Chips—Part II: CIGS Solar Cells

We present the monolithic integration of deep-submicrometer complementary metal-oxide-semiconductor (CMOS) microchips with copper indium gallium (di)selenide (CIGS) solar cells. Solar cells are manufactured directly on unpackaged CMOS chips. The microchips maintain comparable electronic performance, and the solar cells on top show an efficiency of 8.4 ± 0.8% and a yield of 84%, both values being close to the glass reference. The main integration issues, i.e., adhesion, surface topography, metal ion contamination, process temperature, and mechanical stress, can be resolved while maintaining standard photovoltaic processing. A tight process window is found for the manufacturing of CIGS solar cells on the CMOS side of the microchip. More process margin exists for backside integration.

Integration of Solar Cells on Top of CMOS Chips Part I: a-Si Solar Cells

We present the monolithic integration of deep-submicrometer complementary metal-oxide-semiconductor (CMOS) microchips with a-Si:H solar cells. Solar cells are manufactured directly on the CMOS chips. The microchips maintain comparable electronic performance, and the solar cells show efficiency values above 7%. The yield of photovoltaic cells on planarized CMOS chips is 92%. This integration allows integrated energy harvesting using established process technologies and, as such, is an important step toward wireless autonomous microsystems (i.e., “smart dust”).

Low Phase Noise and Low Power Consumption VCOs Using CMOS and IPD Technologies

This paper presents two voltage controlled oscillators (VCOs) operating at 5.42 and 5.76 GHz implemented in 0.18-μm complementary metal-oxide semiconductor (CMOS) technology with integrated passive device (IPD) inductors. One IPD inductor was stacked on the top of the active region of the 5.76-GHz VCO chip, whereas the other IPD inductor was placed on the top of the 5.42-GHz VCO CMOS chip but far from the its active region. The high-quality IPD inductors reduce the phase noise of the VCOs. The measurements of the two VCOs indicate the same phase noise of -120 dBc/Hz at 1 MHz offset frequency. These results demonstrate a 6-dB improvement compared to the VCO using an on-chip inductor. This paper also presents the effect of the coupling between the IPD inductor and the active region of the chip on the phase noise performance.

Waveguide biosensor with integrated detector array for tuberculosis testing

A label-free immunoassay using a local evanescent array coupled (LEAC) biosensor is reported. Complementary metal oxide semiconductor chips with integrated photoconductor arrays are used to detect an antibody to a M. tuberculosis protein antigen, HspX. The metrology limits of the LEAC sensor using dc and ac measurement systems correspond to average film thicknesses of 28 and 14 pm, respectively. Limits of detection are 87 and 108 pm, respectively, for mouse immunoglobulin G antibody patterning and antigen detection.

Pyramid Architecture for 3840 X 2160 Quad Full High Definition 30 Frames/s Video Acquisition

Image pipeline processing is crucial to generating high quality images in applications using complementary metaloxide-semiconductor (CMOS)/charge-coupled device sensors. The on-chip line buffer normally dominates the total area and power dissipation due to the needed filter window buffering. As image resolution and filter support increase, the area and power requirement increase accordingly. This paper presents a novel pyramid architecture to efficiently process a system that the image pipeline is between an image sensor and video coding engine. By utilizing the features of the pyramid structure and block-based video/image encoders, the proposed architecture is scalable from low to high image resolution and filter size. The input image is first partitioned into floors of tiles to reduce the frame line buffer. Two computing schemes, immediate result reuse and vertical snack scan, are utilized to reduce the overlapping redundant computations. A 90 nm CMOS chip design with 7 × 5 filter support for 3840 × 2160 quad full high definition video at 30 frames/s is designed to demonstrate the performance of power and area efficiency. Compared with traditional architectures with frame line buffers, the proposed design has shown that the power consumption is reduced by 25% to 108 mW from 145 mW. The chip area is reduced by 65% to 309 K from 888 K logic gates. The external memory bandwidth increases to 8286 Mbit/s from 5972 Mbit/s for YUV4:2:0, from 7963 Mbit/s for YUV4:2:2, and is reduced by 30% from 11944 Mbit/s for YUV4:4:4.