NoC Communication Research Articles

A comprehensive evaluation approach for efficient countermeasure techniques against timing side-channel attack on MPSoC-based IoT using multi-criteria decision-making methods

ContextTiming side-channel attack countermeasure techniques (TSCA-CTs) evaluation is a multi-criteria decision-making (MCDM) problem based on different MPSoCs of IoT platform architectures, performance, and design overhead. Therefore, the Fermatean by fuzzy decision opinion score method (F-FDOSM) for prioritizing the powerful countermeasure technique against timing side-channel attack is the best approach because it employs the most efficient MCDM ranking technique. Nonetheless, the FDOSM method needs to weigh the criteria before being submitted for the ranking process. In order to address this theoretical challenge, the Criteria-importance through inter-criteria correlation (CRITIC) technique can be applied as an effective MCDM weighting technique to offer an explicit weight for a set of criteria with no inconsistency based on the standard deviation, which uses correlation analysis to determine the relevance of each criterion. ObjectivesThis research proposes a Fermatean-FDOSM framework for evaluating TSCA-CTs in the context of MPSoCs-based IoT and CRITIC techniques to weight the criteria. MethodsThe methodology is presented in three phases. Firstly, a proposed countermeasure techniques dataset was collected that included seven defense approaches (e.g., Gossip and SER router) based on ten criteria (e.g., number of malicious IP cores, number of routers, power, latency… etc.). Then, the decision matrix was built based on an intersection of the countermeasure techniques as an alternative and MPSoC design and performance criteria. Then, the multi-criteria decision-making methods were integrated. The CRITIC method for criteria weighting was followed by the development of the Fermatean-FDOSM method for ranking. Results(1) CRITIC weighting shows that MPSoC NoC throughput (packet/clock) is the highest weight criterion, whereas latency (clock/cycle) is the less weight criterion. (2) The Fermatean-FDOSM-based group ranking shows that the Adaptive routing countermeasure technique is the highest score alternative compared to the Combined with separate interface hybrid approach. (3) The TSCA-CTs priority ranks were subjected to a systematic ranking that was confirmed by strong correlation results throughout ten criterion weight values. A comparison with recent studies confirmed the feasibility of the proposed framework. ConclusionThe outcomes of this study are anticipated to give particular knowledge and direction to those who want to do decision theory-based MPSoCs-based IoT and NoC communication security research.

Evaluation Approach for Efficient Countermeasure Techniques Against Denial-of-Service Attack on MPSoC-Based IoT Using Multi-Criteria Decision-Making

Context: Denial-of-Service Attack countermeasure techniques (DoS A-CTs) evaluation is a Multi-criteria decision-making (MCDM) problem based on different MPSoCs of IoT platform design, performance, and design overhead. Therefore, the Fermatean by fuzzy decision opinion score method (F-FDOSM) for prioritizing the powerful countermeasure technique against Denial-of-Service (DoS) attack is the best approach because it employs the most efficient MCDM ranking technique. Nonetheless, the FDOSM method needs to weight the criteria before being submitted for the ranking process. In order to address this theoretical challenge, the Criteria-importance through inter-criteria correlation (CRITIC) technique can be applied as an effective MCDM weighting technique to offer an explicit weight for a set of criteria with no inconsistency based on the standard deviation, which uses correlation analysis to determine the relevance of each criterion. Objectives: This research proposes a Fermatean-FDOSM framework for evaluating DoS A-CTs in the context of MPSoCs-based IoT and CRITIC techniques to weight the criteria. Methods: The methodology is presented in three phases. Firstly, a proposed countermeasure techniques dataset was collected that included eighteen defense approaches (e.g., Sniffer, SeRA, and RLAN) based on thirteen criteria (e.g., size, power, latency, and effectiveness…etc.). Then, the Decision matrix (DM) was built based on an intersection of the countermeasure techniques as an alternative and MPSoC design and performance criteria. Then, the multi-criteria decision-making methods were integrated. The CRITIC method for criteria weighting was followed by the development of the Fermatean-FDOSM method for ranking. Results: (1) CRITIC weighting shows that MPSoC NoC Routing Algorithm (XY and YX) is the highest weight criterion, whereas latency (clock/cycle) is the less weight criterion. (2) The Fermatean-FDOSM-based group ranking shows that the Collision Point Router Detection (CPRD) countermeasure technique is the first-ranked alternative compared to the Secure Model Checkers (SMCs) approach. (3) The DoS A-CTs priority ranks were subjected to a systematic ranking that was confirmed by solid correlation results throughout thirteen criterion weight values. A comparison with recent studies confirmed the feasibility of the proposed framework. Conclusion: The results of this research are expected to provide a specific understanding and guide for those who want to engage in MPSoCs-based IoT and NoC communication security research with decision theory.

Energy efficient 3D network-on-chip based on approximate communication

Technology advancement and integration of many cores into a chip lead to high-performance parallel architectures in computing systems. Three-dimensional Network-on-Chips (3D NoCs) have been adopted as a promising architecture in the communication of many-core systems and present lower latency and area compared to 2D NoCs, and they introduce the higher performance. However, 3D NoCs possess thermal challenges due to the high power consumption of 3D routers. The approximation can be used in communication in NoCs to reduce the congestion and latency in the network in error-tolerant applications. In this paper, we employ an approximation mechanism to truncate data packets based on the approximate nature of their applications. So, we reduce network congestion, data volume on communication, and latency. This approach makes it possible to use energy-saving methods in an efficient way, as the network congestion and resource workload are decreased. To show the approach, after employing approximation in communication, we modify the architecture of the routers and links by applying the voltage scaling technique, which is controlled based on the network congestion and approximate regions of the applications. Therefore, the amount of energy saving due to employing the voltage scaling is significantly increased, which alleviates the thermal problems in 3D NoCs. Simulation results indicate that our approach reduces the energy consumption by 21.6% while reducing the latency by 22% compared to some related works for NoCs, with only about 1.3% hardware overhead.

A Review of Design Approaches for Enhancing the Performance of NoCs at Communication Centric Level

As the trend of technology shrinking continues a vast amount of processors are being incorporated in a limited space. Due to this almost half of the chip area in Multi-Processor Systems-on-Chips (MPSoCs) is under interconnections, which pose a big problem for communication. Network-on-Chips (NoCs) evolved as a significant scalable solution for removing wiring congestion and communication problem in MPSoCs. NoCs provide the advantage of customized architecture, increased scalability and bandwidth. NoC is a structured framework where communication is the prime concern. In this review paper we present an overview of research and design approaches in the communication centric areas of NoCs. Here we have tried to discuss and iterate most of the available work done for communication in 2D NoCs. This paper gives the insight of different attributes and performance parameters of NoCs. Further it gives a detailed description of how topology, flow control and routing mechanisms can affect the qualitative aspects (performance) of NoCs. It then explains how various attributes of routing can help in increasing the efficacy of NoCs. Subsequently a brief review of different simulators used for NoCs is given. All of this is provided based on the survey of academic, theoretical and experimental approaches presented in the past. Finally some suggestions for future work are also given.

Shortest Path Search Algorithm in Optimal Two-Dimensional Circulant Networks: Implementation for Networks-on-Chip

For a family of optimal two-dimensional circulant networks with an analytical description, two new improved versions of the shortest path search algorithm with a constant complexity estimate are obtained. A simple, based on the geometric model of circulant graphs, proof of the formulas used for the shortest path search algorithm is given. Pair exchange algorithms are presented, and their estimates are given for networks-on-chip (NoCs) with a topology in the form of the considered graphs. New versions of the algorithm improve the previously proposed shortest path search algorithm for optimal generalized Petersen graphs with an analytical description. The new proposed algorithm is a promising solution for the use in NoCs which was confirmed by an experimental study while synthesizing NoC communication subsystems and comparing the consumed hardware resources with those when other previously developed routing algorithms.

Interference Analysis for Optical Wireless Communications in Network-on-Chip (NoC) Scenarios

Optical wireless (OW) communications, besides being of great interest for indoor and outdoor applications, have been recently proposed as a powerful alternative to the existing wired and wireless radio frequency (RF) interconnects in a network-on-chip (NoC). Design and analysis of networks with OW links require a careful investigation of cross-link interference, which impacts considerably the efficiency of systems that reuse the same channel for multiple transmissions. Yet, there is no comprehensive analysis of interference for OW NoCs, and the analyses of crosstalk in optical waveguide communications usually rely on synchronous data transmissions. A novel framework for the analysis of on-chip OW communications in the presence of cross-link cochannel interference and noise is proposed, where asynchronous data transmissions are considered. Self-beating of interfering signals is also considered, which was often neglected in previous literature. The bit error probability (BEP) for arbitrary number of interfering sources is derived as a function of signal-to-noise ratio (SNR), interference powers, detection threshold and pulse shaping, using both exact and approximation methods. The proposed analysis can be applied to both noise- and interference-limited cases, and enables a system designer to evaluate reuse distance between links that share the same optical carrier for simultaneous communication in NoCs.

Wireless Network On-Chips History-Based Traffic Prediction for Token Flow Control and Allocation

Wireless network-on-chip (WiNoC) uses a wireless backbone on top of the traditional wired-based NoC which demonstrated high scalability. WiNoC introduces long-range single-hop link connecting distanced core and high bandwidth radio frequency interconnects that reduces multi-hop communication in conventional wired-based NoC. However, to ensure full benefits of WiNoC technology, there is a need for fair and efficient Medium Access Control (MAC) mechanism to enhance communication in the wireless Network-on-Chip. To adapt to the varying traffic demands from the applications running on a multicore environment, MAC mechanisms should dynamically adjust the transmission slots of the wireless interfaces (WIs), to ensure efficient utilization of the wireless medium in a WiNoC. This work presents a prediction model that improves MAC mechanism to predict the traffic demand of the WIs and respond accordingly by adjusting transmission slots of the WIs. This research aims to reduce token waiting time and inefficient decision making for radio hub-to-hub communication and congestion-aware routing in WiNoC to enhance end to end latency. Through system level simulation, we will show that the dynamic MAC using an History-based prediction mechanism can significantly improve the performance of a WiNoC in terms of latency and network throughput compared to the state-of-the-art dynamic MAC mechanisms.

Side-channel protected MPSoC through secure real-time networks-on-chip

The integration of Multi-Processors System-on-Chip (MPSoCs) into the Internet-of-Things (IoT) context brings new opportunities, but also represent risks. Tight real-time constraints and security requirements should be considered simultaneously when designing MPSoCs. Network-on-Chip (NoCs) are specially critical when meeting these two conflicting characteristics. For instance the NoC design has a huge influence in the security of the system. A vital threat to system security are so-called side-channel attacks based on the NoC communication observations. To this end, we propose a NoC security mechanism suitable for hard real-time systems, in which schedulability is a vital design requirement. We present three contributions. First, we show the impact of the NoC routing in the security of the system. Second, we propose a packet route randomisation mechanism to increase NoC resilience against side-channel attacks. Third, using an evolutionary optimisation approach, we effectively apply route randomisation while controlling its impact on hard real-time performance guarantees. Extensive experimental evidence based on analytical and simulation models supports our findings.

Design of TTL Based Routing Algorithm on UTAR Network on Chip Communication Architecture

XY adaptive routing protocol is a routing protocol used on UTAR NoC communication architecture. This routing algorithm adapts shrotest-path first algorithm, which will forward will not be able to work optimally if the closest route no longer have enough bandwidth to continue the packet. Packet will be stored inside the router and forwarded to the nearest router when closest route has enough bandwidth. This paper suggest TTL based routing algorithm to resolve this issue. TTL based routing algorithm adapts XY adaptive routing protocol by adding several parameters on RTL UTAR NoC and additional bit in each packet sent by router. This additional bit and parameter will be used by TTL based algorithm as additional factors in choosing alternative routes inside the communication architecture. Use of TTL on TTL based routing different from use of TTL on communication network. Packets that carry TTL value that equal to Maximum TTL will be route using XY adaptive routing protocol. TTL based routing algorithm has shown better performance compared to XY adaptive routing on some of the experiment done using MSCL NoC Traffic Pattern Suite. This research also proves that TTL based routing algorithm cannot work optimally on small-scaled architecture.

CAP-W: Congestion-aware platform for wireless-based network-on-chip in many-core era

In order to fulfill the ever-increasing demand for high-speed and high-bandwidth, wireless-based MCSoC is presented based on a NoC communication infrastructure. Inspiring the separation between the communication and the computation demands as well as providing the flexible topology configurations, makes wireless-based NoC a promising future MCSoC architecture. However, congestion occurrence in wireless routers reduces the benefit of high-speed wireless links and significantly increases the network latency. Therefore, in this paper, a congestion-aware platform, named CAP-W, is introduced for wireless-based NoC in order to reduce congestion in the network and especially over wireless routers. The triple-layer platform of CAP-W is composed of mapping, migration, and routing layers. In order to minimize the congestion probability, the mapping layer is responsible for selecting the suitable free core as the first candidate, finding the suitable first task to be mapped onto the selected core, and allocating other tasks with respect to contiguity. Considering dynamic variation of application behaviors, the migration layer modifies the primary task mapping to improve congestion situation. Furthermore, the routing layer balances utilization of wired and wireless networks by separating short-distance and long-distance communications. Experimental results show meaningful gain in congestion control of wireless-based NoC compared to state-of-the-art works.

Extending Real-Time Analysis for Wormhole NoCs

The delay upper-bound analysis problem is of fundamental importance to real-time applications in Network-on-Chips (NoCs). In the paper, we revisit two state-of-the-art analysis models for real-time communication in wormhole NoCs with priority-based preemptive arbitration and show that the models only support specific router architectures with large buffer sizes. We then propose an extended analysis model to estimate delay upper-bounds for all router architectures and buffer sizes by identifying and analyzing the differences between upstream and downstream indirect interferences according to the relative positions of traffic flows and taking the buffer influence into consideration. Simulated evaluations show that our model supports one more router architecture and applies to small buffer sizes compared to the previous models.

Architecture level analysis for process variation in synchronous and asynchronous Networks-on-Chip

Synchronous NoCs suffer from performance degradation due to clock skew. Clock skew is more pronounced with process variation (PV). Although asynchronous NoCs suffer from handshaking overhead, their immunity to PV is better than synchronous networks which would favor them in terms of throughput. Architecture-Level analysis aims to determine the ability of different NoC communication schemes to mitigate the impact of PV. The proposed analysis depends on redeveloped simulator which is unique PV-aware simulator for both synchronous and asynchronous NoCs.Architecture-Level simulation shows that clock skew causes significant performance degradation in synchronous networks. Clock skew represents 27% and 32% of the delay variation for 45 nm and 32 nm technologies, respectively. Using real traffic, Architecture-Level analysis shows considerable throughput reduction for synchronous NoC under PV conditions. Throughput degradation of synchronous NoC increases rapidly with technology scaling down. 64-Cores synchronous NoC loses 30% of the nominal throughput for 45 nm technology and 41% of throughput for 32 nm with PV. On the other hand, 64-Cores asynchronous network throughput degradation is 12% and 13.6% for 45 nm and 32 nm technologies, respectively. For different NoC dimensions and using different workloads, throughput reduction for synchronous design is more than double the reduction of asynchronous design. Asynchronous scheme is preferable as technology scales.

An efficient network on-chip architecture based on isolating local and non-local communications

In this paper, a locality aware NoC communication architecture is proposed. The architecture may reduce the energy consumption and latency in MultiProcessor Systems on Chips (MPSoCs). It consists of two network layers which one layer is dedicated to the packets transmitted to near destinations and the other layer is used for the packets transmitted to far destinations. The actual physical channel width connecting the cores is divided between the two layers. The locality is defined based on the number of hops between the nodes. The relative significances of the two types of communications determine the optimum ratio for the channel width division. To assess the efficiency of the proposed method, we compare its communication latency with that of conventional one for different channel widths, communication traffic profiles, and mesh sizes.

Differentiated Communication Services for NoC-Based MPSoCs

The adoption of Networks-on-Chip (NoCs) as the communication infrastructure for complex integrated systems is a fact, and has been promoted by the growing number of processing elements integrated in current MPSoCs. These are designed to execute several applications in parallel, with different communication requirements and distinct levels of required quality of service. To meet these restrictions, most designs customize the MPSoC at design time, using specific NoC communication services as adaptive routing algorithms, priorities, and connections. However, MPSoCs are increasingly used in embedded systems, where new applications may be added at runtime, characterizing dynamic workload scenarios. Such scenarios require adaptability at runtime, with applications having the possibility to select the most appropriate communication service according to their respective requirements. The goal of the present work is to link the hardware level of NoCs to the MPSoC application level, proposing the development of a communication API that exposes the communication services offered by the NoC to the application developer. Executing real and synthetic applications in two different MPSOCs, and using four different NoC communication services enabled to demonstrate the efficiency of the proposed approach to meet applications requirements.

CDMA Technique with Inter-process Communication

A novel implementation of Inter process communication in CDMA NOC is proposed. In this study, the orthogonality properties of a Walsh code are used to route data packets between the IP-Cores.The asynchronous circuit design with combinational logic (Gate level design) is used for transmission and receiving circuits, along with ip-cores and reduces the processing time and resource utilization. The use of asynchronous pipelined core design process increases the operating frequency as well. The data transfers over IP-Core based interconnect is implemented on gate level. The latency and throughput values are obtained for variable payload size. The performance of asynchronous and synchronous communication are measured and analyzed.

A reliable and power efficient flow-control method to eliminate crosstalk faults in network-on-chips

This paper proposes a power-efficient flow-control method to tackle the problem of crosstalk faults in Network-on-Chips (NoCs). The method, called FRR (Flit Reordering/Rotation), combines three coding mechanisms to entirely eliminate opposite direction transitions (OD transitions) as the source of crosstalk faults in NoC communication channels. The first mechanism, called flit-reordering, reorders flits of every packet to find a flit sequence which produces the lowest number of OD transitions on NoC channels. The second mechanism called flit-rotation, logically rotates the content of every flit of the packet with respect to previously sent flit to achieve even more reduction in the number of OD transitions. Finally, the third mechanism called flit-insertion, investigates flits of the packet to find the OD transitions which are not removed by first and second mechanisms. This mechanism inserts null-flits between the required flits to completely eliminate appearance of OD transitions on NoC channels. Evaluation of FRR method is done in two ways: (1) VHDL-based simulations are carried out for 16- and 32-bit channels when maximum reorderings and maximum rotations in the first and second mechanisms are limited to 2, 4, and 8. (2) An analytical model is developed to calculate and compare the expected number of OD transitions in an unprotected NoC as well as an FRR-enabled NoC. Both simulation and analytical results confirm that the FRR method completely removes crosstalk faults from NoC channels. In addition, VHDL simulations show that the FRR method provides a remarkable power saving, since the method reduces the number of transitions in NoC channels by at least 32.8%.

A Fault-Tolerant Router's Simulation and Design Based-FPGA in Network-on-Chips

Network-on-Chip has become a hot spot in the field of complex System-on-Chip for its effectiveness. The performance of NoC, to a large extent, depends on the router's structure. In this paper, we present a method based on fault-tolerant hardware structure to solve the problem of instability inhere in routers. We suggest adding bypass into routers and using a dynamic reconfigurable XY-YX routing algorithm; this solution shall ensure effective communications in NoC. Verilog language is used to describe all of the modules in Quartus II environment. We conduct the simulation experiment and area integrated, as well as accomplishes the overall modules’ design using Altera's FPGA. The experiment results show that our design can meet the needs of communication in NoC.

An analytical model of broadcast in QoS-aware wormhole-routed NoCs

Networks-on-Chip (NoC) emerged to address the technological and design issues related to development of large systems-on-chip (SoCs). Due to diversity of the application's performance requirements, most NoC architectures offer supports for quality of service (QoS). Also, to utilize the available bandwidth efficiently, they might implement mechanisms for delivering collective communication operations. This paper presents an analytical model to predict the average latency of wormhole-routed prioritized broadcast communication in NoCs. The model assumes that the network uses all-port routers scheme and offers differentiated services-based QoS. To verify the analysis, the model predictions are compared against the results obtained from a discrete-event simulator developed using OMNET++.

Application of deterministic and stochastic Petri-Nets for performance modeling of NoC architectures

The design of appropriate communication architectures for complex Systems-on-Chip (SoC) is a challenging task. One promising alternative to solve these problems are Networks-on-Chip (NoCs). Recently, the application of deterministic and stochastic Petri-Nets (DSPNs) to model on-chip communication has been proven to be an attractive method to evaluate and explore different communication aspects. In this contribution the modeling of basic NoC communication scenarios featuring different processor cores, network topologies and communication schemes is presented. In order to provide a testbed for the verification of modeling results a state-of-the-art FPGA-platform has been utilized. This platform allows to instantiate a soft-core processor network which can be adapted in terms of communication network topologies and communication schemes. It will be shown that DSPN modeling yields good communication performance prediction results at low modeling effort. Different DSPN modeling aspects in terms of accuracy and computational effort are discussed.

"It's a small world after all": NoC performance optimization via long-range link insertion

Networks-on-chip (NoCs) represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered so far are based on either completely regular or fully customized topologies. In this paper, we present a methodology to automatically synthesize an architecture which is neither regular nor fully customized. Instead, the communication architecture we propose is a superposition of a few long-range links and a standard mesh network. The few application-specific long-range links we insert significantly increase the critical traffic workload at which the network transitions from a free to a congested state. This way, we can exploit the benefits offered by both complete regularity and partial topology customization. Indeed, our experimental results demonstrate a significant reduction in the average packet latency and a major improvement in the achievable network through with minimal impact on network topology