Architecture level analysis for process variation in synchronous and asynchronous Networks-on-Chip

Abstract

Synchronous NoCs suffer from performance degradation due to clock skew. Clock skew is more pronounced with process variation (PV). Although asynchronous NoCs suffer from handshaking overhead, their immunity to PV is better than synchronous networks which would favor them in terms of throughput. Architecture-Level analysis aims to determine the ability of different NoC communication schemes to mitigate the impact of PV. The proposed analysis depends on redeveloped simulator which is unique PV-aware simulator for both synchronous and asynchronous NoCs.Architecture-Level simulation shows that clock skew causes significant performance degradation in synchronous networks. Clock skew represents 27% and 32% of the delay variation for 45 nm and 32 nm technologies, respectively. Using real traffic, Architecture-Level analysis shows considerable throughput reduction for synchronous NoC under PV conditions. Throughput degradation of synchronous NoC increases rapidly with technology scaling down. 64-Cores synchronous NoC loses 30% of the nominal throughput for 45 nm technology and 41% of throughput for 32 nm with PV. On the other hand, 64-Cores asynchronous network throughput degradation is 12% and 13.6% for 45 nm and 32 nm technologies, respectively. For different NoC dimensions and using different workloads, throughput reduction for synchronous design is more than double the reduction of asynchronous design. Asynchronous scheme is preferable as technology scales.