Energy efficient 3D network-on-chip based on approximate communication

Abstract

Technology advancement and integration of many cores into a chip lead to high-performance parallel architectures in computing systems. Three-dimensional Network-on-Chips (3D NoCs) have been adopted as a promising architecture in the communication of many-core systems and present lower latency and area compared to 2D NoCs, and they introduce the higher performance. However, 3D NoCs possess thermal challenges due to the high power consumption of 3D routers. The approximation can be used in communication in NoCs to reduce the congestion and latency in the network in error-tolerant applications. In this paper, we employ an approximation mechanism to truncate data packets based on the approximate nature of their applications. So, we reduce network congestion, data volume on communication, and latency. This approach makes it possible to use energy-saving methods in an efficient way, as the network congestion and resource workload are decreased. To show the approach, after employing approximation in communication, we modify the architecture of the routers and links by applying the voltage scaling technique, which is controlled based on the network congestion and approximate regions of the applications. Therefore, the amount of energy saving due to employing the voltage scaling is significantly increased, which alleviates the thermal problems in 3D NoCs. Simulation results indicate that our approach reduces the energy consumption by 21.6% while reducing the latency by 22% compared to some related works for NoCs, with only about 1.3% hardware overhead.