Common Mode Transient Immunity Research Articles

A 25 Mbps 15 ns Propagation Delay 150 kV/μs CMTI Configurable Dual-Channel Capacitive Digital Isolation Driver.

Electrical isolation devices are essential components for safeguarding the reliability of electronic systems under harsh conditions. Digital isolators are widely used in low-power circuits due to their high immunity to disturbances. In this paper, a capacitive digital isolator for high-efficiency power supply scenarios is proposed with a high common-mode transient immunity (CMTI) and high data transmission rate. The on-off keying (OOK) modulation technique is used to ensure a high speed and accurate signal transmission. A fully integrated high-voltage level-shift driver with an ns-scale delay is proposed for increasing the drive capacity. Post-simulation results in Cadence IC 6.1.7 with the standard 0.18 μm CMOS process show that the proposed architecture achieves a 25 Mbps data transmission rate and 15 ns typical propagation delay with output peak currents of 2 A/4 A, respectively. Meanwhile, a CMTI of more than 150 kV/μs is realized.

A Through-Power-Link Hysteretic-Controlled Capacitive Isolated DC–DC Converter With Enhanced Efficiency and Common-Mode Transient Immunity

A Through-Power-Link Hysteretic-Controlled Capacitive Isolated DC–DC Converter With Enhanced Efficiency and Common-Mode Transient Immunity

A Monolithic GaN Power Stage with Common-Mode Transient Immunity and Negative Voltage Operation Design for High Frequency Power Converters

A Monolithic GaN Power Stage with Common-Mode Transient Immunity and Negative Voltage Operation Design for High Frequency Power Converters

A Fully Integrated 0.6 Gbps Data Communication System for Inductive-Based Digital Isolator with 0.8 ns Propagation Delay and 10−15 BER

Digital isolators are implemented to protect low-voltage electronics and ensure human safety during high-voltage surge events. In this work, we present the design of an inductive-based digital isolation system that can sustain up to 1 kVrms breakdown voltage. The proposed system is designed using the pulse polarity modulation scheme and fabricated in a 0.35 μm CMOS. Two identical dies are bounded within the IC package, with one die housing the transmitter (Tx) and the isolation transformer, while the other die contains the receiver (Rx). Two different customized designs between three metal layers are implemented to form the isolation element. The transformer’s secondary coil is constructed in metal-1, while the primary coil is formed in metal-2 and metal-3 for comparing the system functionality, isolation capability, and propagation delay. The functionality has been verified by measurements for an operating frequency of 300 MHz with a 2.6 ns propagation delay and an energy consumption of 8.15 × 103 pJ/bit at 1 Mbps. The chip was tested under extreme temperatures and achieved a maximum measured common mode transient immunity (CMTI) of 500 V/μs. Jitter has been examined to ensure fast transmission at a bit error rate (BER) of 10−15 with a total jitter (TJ) of 188.18 ps.

A capacitively coupled digital isolator with CMTI of 160 kV/μs and data rate of 230 Mbps

—This paper presents a capacitively coupled digital isolator with superior Common Mode Transient Immunity (CMTI) and high performances. This work adopts the On-Off Keying (OOK) architecture to cancel the influence of Common Mode Transient (CMT) and increase the speed performances. In addition, it adopts a fast-transient-response architecture for the Schmitt trigger to further improving the speed performances. Besides, this work proposes a gate-cross-coupled common-gate pre-amplifier with an active zero load, amplifying the signal after the isolation capacitance. By applying the proposed technique, the high-frequency gain retains to high value, while the low-frequency gain is greatly attenuated. It employs an envelope-comparator, an integrator and a filter as demodulator to reduce the propagation delay and speed up the data rate. Fabricated in a 0.18 μm CMOS process, the chip achieves 160 kV/μs CMTI, 230 Mbps data rate, 6 ns propagation delay, 1.5 mA dynamic current and 14 kV isolation breakdown voltage with the area of the isolation capacitance of 2 × 104 μm2.

A capacitively coupled digital isolator using multiple-pulse-coding architecture with CMTI of 200kV/μs and static current of 60μA

This paper presents a capacitively coupled digital isolator with low power consumption and superior Common Mode Transient Immunity (CMTI). It proposes a multiple-pulse-coding architecture and a receiver with an adaptive architecture, which improve the transmission accuracy, eliminate the CMT and achieve low power consumption. The multiple-pulse-coding characterizes edge signal with multi-pulses. The receiver consists of an adaptive pre-amplifier and an adaptive comparator. Fabricated in a 0.18 μm CMOS process, the chip achieves 200 kV/μs CMTI, 60 μA static current, 250 μA dynamic current and 14 kV isolation breakdown voltage with the area of the isolation capacitance of 2×104 μm2.

Equivalent Circuit Model of a Pulse Planar Transformer and Endurance to Abrupt dv/dt

Wide-bandgap (WBG) semiconductor materials offer faster and more reliable power electronic components in electric energy conversion systems. However, their faster switching speed and abilities to operate at higher frequency than silicium devices have brought new challenges, such as electromagnetic interference (EMI) issues. In gate driver applications, EMI issues must be tackled given the close proximity between gate driver systems and WBG power modules. This article focuses on planar pulse transformers for gate drivers in high power applications (3.3 kV, 500 A SiC module). This article tries to give a standard procedure to design, then, simulate pulse transformers with their electrostatic shielding. First, a design guideline using Altium designer is proposed to respect the European standards. A method to extract the transformer design from Altium to Ansys is also proposed. Finally, a frequency analysis is discussed to use in Ansys simulations and parameters extraction. Tests have been performed to check the proposed transformer’s electromagnetic compatibility immunity under a 125 kV μs^−1 common mode transient immunity test.

A MHz-Pulse-Transformer Isolated Gate Driver With Signal-Power Integrated Transmission for Medium-Voltage SiC MOSFETs

The conventional isolated gate driver (GD) solution for the medium-voltage (MV) SiC <small>mosfet</small> separates the signal and power transmissions and requires a bulky GD power supply (GDPS). This article presents a signal-power integrated GD for MV SiC <small>mosfet</small>s with a compact footprint. The proposed GD transmits both the pulsewidth modulation (PWM) signal and GD power by 20-MHz modulated class-E resonant flyback converters, where the transmitted GD power can maintain constant within the full PWM duty-cycle range (i.e., 0&#x0025;&#x2013;100&#x0025;). In addition, the PWM signal transmission of the proposed GD achieves a low total propagation delay time &lt; 75 ns by utilizing the fast transient of 20-MHz RFCs and the edge-based envelope detector. A printed-circuit-board-based coreless transformer is integrated into the proposed GD to achieve an insulation voltage higher than 10 kV_RMS and a low coupling capacitance of 5.85 pF. The common-mode transient immunity of proposed GD is higher than 100 V&#x002F;ns, which is beneficial to drive MV SiC <small>mosfet</small>s with high <i>dv&#x002F;dt</i>. The proposed GD does not require additional GDPSs nor fiber-optics, which achieves a smaller size compared to conventional isolated GDs and is promising to be integrated into SiC <small>mosfet</small> module packages. Experimental results on 3.3 kV and 10 kV SiC <small>mosfet</small>s are provided to validate the effectiveness of the proposed GD.

A 650 kV/μs Common-Mode Resilient CMOS Galvanically Isolated Communication System

This work presents a galvanically isolated chip-to-chip communication system that utilizes laterally coupled resonators in combination with a new differential full-wave receiver architecture. Lateral resonant coupling increases the isolation capability and significantly minimizes the intra-chip coupling capacitance of galvanic isolators beyond the limits of vertical coupling in standard CMOS. The presented system marries the merits of a laterally resonant coupled channel with a source-gate coupled low-power, low-latency RF detector architecture that enables high common-mode and differential noise immunity. A center-tapped transformer is used as the interface between the proposed fully differential receiver and the communication channel to further enhance the common-mode transient immunity (CMTI). The proposed system is integrated in a 0.25 μm CMOS process with four metal layers and does not alter the native process or necessitate additional fabrication steps. The design does not require exotic packaging and achieves state-of-art CMTI of 650 kV/μs at 5 kVpk isolation, sub-20ns propagation delay, and maintains a small form-factor of 0.95 mm². The GI system exhibits robust performance to fabrication variations, with less than ±0.3% and ±8% sensitivity to process variation and post-assembly chip distance offset, respectively.

Package-Scale Galvanic Isolators Based on Radio Frequency Coupling: Micro–Antenna Design

This paper presents the design of on-chip micro-antennas for package-scale galvanic isolators based on RF planar coupling. A step-by-step design procedure is proposed, which aims at the maximization of the weak electromagnetic coupling between the RX and TX antennas integrated on side-by-side co-packaged chips to enable both high isolation rating and common-mode transient immunity thanks to the high dielectric strength and low capacitive parasitics of a molding compound-based galvanic barrier, respectively. Micro-antenna design guidelines are drawn, highlighting the main relationship between coil coupling performance and their layout parameters, which are often in contrast with respect to traditional integrated inductor ones.

A Small Footprint Digital Isolator Based on CMOS Integrated Hall-Effect Sensor

Digital isolators have been widely used to protect low voltage electronics as well as human safety from high voltage surges. However, conventional isolation links occupy large chip areas. In this article, a novel small-size on- chip digital isolator for medium-bitrate application based on a CMOS integrated Hall-effect sensor is reported. With the proposed approach, the area of the transmitter coil is reduced to lower than 50% of conventional transformers. The architecture reduces the chip area in isolation amplifiers, power control units, DC-DC converters, and clock recovery circuits. It allows the integration of multichannel isolators using two custom integrated circuits with no post-processing. The tested prototype achieves a data transfer rate of 20 Mbps with above 12 kV/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> of common-mode transient immunity (CMTI). It has 900 V of continuous isolation working voltage, 27 ns propagation delay, and consumes 2.3 mA of static current.

High-Scalability Enhanced Gate Drivers for SiC MOSFET Modules With Transient Immunity Beyond 100 V/ns

Silicon-carbide (SiC) transistors with growing readiness for the power converter market have raised an emerging need for high-performance gate driver (GD) units to maximize their remarkable characteristics. In particular, the GD units for the SiC devices that experience extremely fast commutations at the medium-voltage level require powerful driving capability, effective short-circuit (SC) protection, and superb common-mode transient immunity. Thereby, this article presents a systematic enhanced GD (eGD) solution that incorporates three scalable features compatible with almost all the SiC mosfet modules. First, a BJT-based multicell current booster is proposed to attain balanced high driving current, low losses, gate-loop inductance less than 1 nH, and great cross-talk immunity. Second, a nonintrusive Rogowski switch-current sensor with high bandwidth and fair accuracy is developed, capable of detecting SC fault in 86 ns and softly turning off 5 kA SC current in 1 $\mu$ s. Third, two noise-free isolation architectures are proposed to mitigate common-mode noise-admittance by more than 100 dB. Fundamentals, analytical designs, experimental validations, and scalability discussions of the three techniques are elaborated, respectively. Finally, a 6-kV, 84-A, and 102-V/ns continuous pump-back test is demonstrated, for the first time, to verify the eGD's excellent performance.

A CMOS Data Transfer System Based on Planar RF Coupling for Reinforced Galvanic Isolation with 25-kV Surge Voltage and 250-kV/µs CMTI

This paper exploits an effective approach to overcome the breakdown limitations of traditional galvanic isolators based on chip-scale isolation barriers, thus achieving a very high isolation rating (i.e., compliant with the reinforced isolation requirements). Such an approach is based on radio frequency (RF) planar coupling between two side-by-side co-packaged chips. Standard packaging along with proper assembling techniques can be profitably used to go beyond 20-kV surge voltage without using expensive or exotic isolation components. As a proof of concept, a bidirectional data transfer system based on RF planar coupling able to withstand an isolation rating as high as 25 kV has been designed in a low-cost standard 0.35-µm CMOS technology. Experimental measurements demonstrated a maximum data rate of 40 Mbit/s using a carrier frequency of about 1 GHz. The adopted approach also guarantees a common mode transient immunity (CMTI) of 250 kV/µs, which is a first-rate performance in view of next generation galvanic isolators for wide-bandgap power semiconductor devices, such as gallium nitride high-electron mobility transistors (GaN HEMTs) and silicon carbide (SiC) MOSFETs.

GaN-based Matrix Converter Design with Output Filters for Motor Friendly Drive System

This paper introduces a gallium nitride (GaN) high electron mobility transistor (HEMT)-based matrix converter for motor friendly drive systems. A fast switching characteristic of the GaN devices causes high dv/dt. This increases the importance of noise immunity and the reduction of parasitic components in system design. In addition, the high dv/dt in motor drive systems leads to voltage spike at a motor input terminal and leakage current through a motor chassis. Accordingly, a gate drive circuit consists of devices with a high common mode transient immunity. A printed circuit board was designed to minimize parasitic inductance, which was analyzed by performing simulations. To mitigate the dv/dt of the voltage applied to the motor and the leakage current, a dv/dt filter and a sine-wave filter were utilized as an output filter of the matrix converter. The effectiveness of each filter was verified by driving an induction motor.

Active common‐mode filter for capacitive‐coupled isolated signalling

Capacitive coupling is a well-established principle in isolated signalling. A major challenge esp. in power electronics is common-mode transient immunity caused by the displacement currents at the coupling capacitors. Digital isolator integrated circuits (ICs) employ modulated signalling, the authors propose an active filter circuit to remove common-mode components from baseband signals. This allows for reliable data transmission during transients in power semiconductor control, AC-coupled RS-485 or transformer-less Ethernet. The filter structure is simple and consists of two current mirrors, one for positive transients, and one for the negative. A current on one differential signal line is ‘mirrored’ onto the other, common-mode currents are conducted to ground. Differential signals are minimally affected. The proposed filter is verified in simulation and experiment: baseband signalling with 50 Mbps in presence of 30 kV/ burst transients is achieved using discrete semiconductors. Even better results are expected when monolithically embedding the filter in an integrated circuit.

High dv/dt Noise Modeling and Reduction on Control Circuits of GaN-Based Full Bridge Inverters

Wide bandgap semiconductor devices allow higher switching frequency and switching speed for their superior characteristics. However, the ultra-fast switching speed causes severe high dv / dt noise in power conversion systems. High dv / dt induced common mode noise deteriorates the operation of gate drivers and control circuits by capacitive coupling. Since some new-developed gate driver integrated circuits (ICs) have improved the common mode transient immunity capability, control circuits become the limit in achieving higher switching speed. This paper investigates the impact of the high dv / dt noise on the control systems of GaN inverters. An improved propagation model is derived based on a full bridge inverter, and the main paths are analyzed. According to the proposed propagation model, different high dv / dt noise reduction methods, such as the sensing methods, common mode chokes, and isolation barrier capacitance, are compared quantitatively. Sensing methods with high impedance show better performance and small isolation barrier capacitance of the power supply of gate driver ICs are significant for high dv / dt noise reduction. Simulation results are presented based on the Q3D extraction results of the investigated inverter system and a 500-W GaN-based full bridge inverter is built for experimental verification.

A Self-Sustained Circuit Building Block Based on 10-kV Silicon Carbide Devices for High-Voltage Applications

This paper presents a self-sustained circuit building block (CBB) that utilizes 10-kV silicon carbide (SiC) devices as the main switches. The CBB achieves a self-sustained operation by powering the gate drives of its main switches with the energy from its dc bus capacitor. The CBB can serve as one of the submodules in a multilevel converter for high-voltage applications. This paper focuses on the design of the 10-kV SiC device's gate drive and its associated auxiliary power supply (APS). The gate drive and its APS are the major technical challenges in the CBB development. The gate drive in the CBB features a common mode transient immunity (CMTI) over 200 kV/μs and fast protection functions. Its APS is based on an active voltage divider concept and achieves 7-kV input voltage with a simple circuit structure and control scheme. The operational principles and design guidelines of the gate drive and its APS are presented in detail. Test results of the CBB in a double-pulse test setup with a 7-kV dc bus voltage are presented to validate the design. Reliable operation of the CBB is demonstrated under dv/dt up to 100 kV/μs.

Focus on test, measurement, and data acquisition

Focus on test, measurement, and data acquisition

A Novel On-Chip Transformer With Patterned Ground Shield for High Common-Mode Transient Immunity Isolated Signal Transfer

In this letter, a novel on-chip transformer (OCT) with patterned ground shield (PGS) is proposed and demonstrated for high common-mode transient immunity isolated signal transfer. By inserting the PGS between the stacked coils of the OCT, the capacitive coupling between the coils is effectively blocked, whereas the inductive coupling is almost unaffected. Consequently, during common-mode voltage transient, the induced displacement current due to the capacitive coupling is directed to the ground by the PGS instead of going through the secondary coil to affect the output signal. Experimental results show that the proposed OCT with PGS achieved a 27%–92% reduction of the common mode to secondary voltage gain compared to the conventional OCT without sacrificing the inductances, the primary-to-secondary voltage gain, the isolation capability, and the fabrication complexity.