High dv/dt Noise Modeling and Reduction on Control Circuits of GaN-Based Full Bridge Inverters

Abstract

Wide bandgap semiconductor devices allow higher switching frequency and switching speed for their superior characteristics. However, the ultra-fast switching speed causes severe high dv / dt noise in power conversion systems. High dv / dt induced common mode noise deteriorates the operation of gate drivers and control circuits by capacitive coupling. Since some new-developed gate driver integrated circuits (ICs) have improved the common mode transient immunity capability, control circuits become the limit in achieving higher switching speed. This paper investigates the impact of the high dv / dt noise on the control systems of GaN inverters. An improved propagation model is derived based on a full bridge inverter, and the main paths are analyzed. According to the proposed propagation model, different high dv / dt noise reduction methods, such as the sensing methods, common mode chokes, and isolation barrier capacitance, are compared quantitatively. Sensing methods with high impedance show better performance and small isolation barrier capacitance of the power supply of gate driver ICs are significant for high dv / dt noise reduction. Simulation results are presented based on the Q3D extraction results of the investigated inverter system and a 500-W GaN-based full bridge inverter is built for experimental verification.