Common-gate Low-noise Amplifier Research Articles

Graphical Design Approach for UWB Stacked CG LNA Using Inversion Coefficient

The design of ultra-wide-band (UWB) low-noise amplifiers (LNAs) entails a large number of design challenges and tradeoffs, which include sustaining good input matching over a wide bandwidth along with finding a proper compromise between various LNA performance metrics, such as gain, bandwidth, noise figure, power, and linearity. This paper presents a design approach for UWB LNAs based on the inversion coefficient (IC). The proposed approach is a graphical design approach where the proper operating point is chosen based on predefined constraints. A complete systematic solution is presented for the problem of UWB input matching with a high degree of analytical accuracy. The design approach is illustrated through the design of two UWB stacked common-gate LNAs in 65 nm technology. The post-layout simulation results show very good agreement with analytical expectations. The first LNA achieves an S11 better than −8.2 dB over a 27.6 GHz frequency range, a gain of 12.4 dB over a 16.5 GHz bandwidth, a minimum noise-figure, NF, of 4.5 dB, and an IIP3 of −5.2 dBm while consuming only 530 μW. The second LNA achieves an S11 better than −15 dB over an 8.8 GHz frequency range, a gain of 12.5 dB over a 6.8 GHz bandwidth, a minimum NF of 4 dB, and an IIP3 of −4.3 dBm while consuming only 550 μW.

A high linearity wideband common-gate LNA with modified differential inductor

In this paper a modified derivation (MD) wideband common-gate low-noise amplifier (CGLNA) is described, with a noise figure (NF) based on Global Foundries and enhanced linearity and frequency response. It is reported that 0.13-µm CMOS technology. The design Combined with folded cascode with gain boosting LNA and common source stage of conventional split inductor stage. At a frequency of 4 GHz, the LNA circuit achieves a high gain of 22.11 dB with an input return loss of -24.86 dB and a flat NF of 0.3 dB. The linearity parameter IIP3 and 1 dB compression are improved -15.62 dBm and -22.69 dBm.

Quad-channel broadband compact multi-antenna GNSS down-converter for high-reliability navigation

Abstract A high-reliability broadband high-linearity down-converter for multi-antenna global navigation satellite system (GNSS) receiver is presented in this paper. Based on direction-of-arrival estimation, the multi-antenna GNSS receiver can separate the GNSS signals from the interfering signals and suppress harmful broadband radio frequency interferences. To drive the off-chip 50 Ω resistive load and meet the stringent requirements of linearity, a quad-channel down-converter with a broadband common-gate low-noise transconductance amplifier, current-driven passive mixer and novel bridge mode transimpedance driving amplifier have been proposed to contruct the multi-antenna receiver. The operating frequency of this down-converter is from 1.15 to 1.65 GHz, covering all bands for global positioning system (GPS), Beidou navigation satellite system (BDS), global navigation satellite system (GLONASS) and Galileo. The measured results show that the proposed quad-channel down-converter achieves +38 dBm output 3rd order intercept point (OIP3) and +17 dBm OP1dB (output-referred 1 dB compression point), 9.5 dB to 12.9 dB noise figure (NF) across the variable gain of 10 dB to 27 dB and approximately 47 dB channel isolation.

A 26–31 GHz Linearized Wideband CMOS LNA Using Post-Distortion Technique

This paper presents a modified post-distortion (PD) linearization technique for cascode common-gate low noise amplifiers (CG-LNAs) working at high frequencies up to millimeter-wave band. This technique utilizes an auxiliary transistor together with an inter-stage inductor to suppress the third order distortion without degrading gain. The input third order intercept point (IIP3) of the linearized CG-LNA is improved by a factor of up to 12 dB. For demonstration, an mm-wave differential CG-LNA was fabricated based on a 65-nm CMOS process. It achieves 2.4–10.6 dBm IIP3, 9.6–12 dB gain, 5.0–5.45 dB NF over 26–31 GHz and consumes 14.4 mW from a 1.2 V supply.

A 400-μW IoT Low-IF Voltage-Mode Receiver Front-End With Charge-Sharing Complex Filter

This work reports on a low-intermediate frequency (IF) voltage-mode receiver front-end for Internet-of-Things (IoT) applications. Design and noise analysis of an unbalanced gate-boosted common-gate low-noise amplifier (LNA) is presented, showing 50% lower power dissipation compared with the conventional balanced topology. Improved linearity is achieved thanks to channel-selection, consisting of two complex poles centered at 2 MHz IF. The first complex pole is embedded in the passive down-conversion mixer for improved frequency selectivity in front of the baseband voltage amplifier. Built in a 28-nm CMOS process, the proposed front-end occupies an active area of 0.175 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , it is supplied with 1 V and consumes only 400 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> , while showing a minimum noise figure (NF) of 6.8 dB and an out-of-band (OOB) IIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> of −0.35 dBm. The performance meets Bluetooth low-energy (BLE) requirements and is competitive with other sub-mW receivers.

Analysis and Design of Submilliwatt Interference-Tolerant Receivers Leveraging N-Path Filter-Based Translational Positive Feedback

A low-power 2.2-2.4-GHz receiver front end for Internet-of-Things (IoT) applications is presented. The front end consists of a capacitively cross-coupled common-gate low-noise amplifier (CC-CGLNA), with translational positive feedback from baseband to RF through a four-phase switching mixer, providing RF filtering and matching, in conjunction with a 1:4 transformer. A detailed analysis of the architecture is presented, highlighting the design tradeoffs between noise, out-of-band filtering, and power. A prototype integrated circuit, fabricated in 28-nm CMOS, consumes 580 μW of power for the entire receiver front end. With this submilliwatt power consumption, it achieves a noise figure (NF) of 11.9 dB, an in-band IIP3 of -6.5 dBm, and an out-of-band IIP3 of +3.3 dBm.

Multi-Feed Antenna and Electronics Co-Design: An E-Band Antenna-LNA Front End With On-Antenna Noise-Canceling and Gₘ-Boosting

This article presents an E-band low-noise amplifier (LNA) co-designed and co-integrated with an on-chip multifeed antenna for antenna-level LNA noise-canceling and gm -boosting. Different from conventional approaches that view antennas as a simple 50-Ω radiation load, we exploit antennas as multi-feed passive radiating networks with direct onantenna signal conditioning and processing capabilities. Such an antenna-electronics co-design concept can potentially advance wireless front-end performance beyond electronics-only designs and opens the door to a plethora of front-end innovations. We also propose equivalent circuits to model multi-feed antenna systems and elucidate on-antenna signal processing operations. As a proof of concept, we propose an antenna-LNA co-designed architecture and explore the interactions among a common-gate (CG) LNA path, a common-source (CS) LNA path, and a pair of near-field coupled folded slot antennas for on-antenna noise-cancellation and g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -boosting. In the measurements, a true V-factor radiation method is introduced as a new approach to measure the noise figure (NF) of the on-chip multi-feed antenna and LNA/RX integration. Then, we perform the conventional sensitivity-based NF measurement. Both measurements show accurate and consistent NF characterization at high millimeter-wave (mm-Wave). The E-band antenna-LNA front end is implemented in the Globalfoundries 45-nm CMOS SOI process and demonstrates 4.8-dB NF with 2.2-dBm IIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> , achieving the best reported FoM at similar frequencies. Furthermore, over-the-air modulation tests are demonstrated, supporting >10-Gb/s high-fidelity high-order QAM signals over an E-band wireless link.

New noise cancellation topology in common-gate LNAs

In this paper a new approach for designing noise canceling common gate (CG) low noise amplifiers (LNAs) is proposed. This method investigates using inductively degenerated common source (IDCS) stage in parallel with CG stage instead of common source (CS) stage. Considering special specification of IDCS LNA, proposed topology can achieve lower noise figure (NF) and better input impedance matching. Analytical calculation for this topology is performed and the equations to satisfy input impedance matching along with noise cancellation condition are presented. The NF of proposed LNA is also calculated while satisfying these conditions by using the calculation of each noise source's transfer function. To validate theoretical analysis, two different LNAs in X band are designed and optimized. The simulations are performed using Advanced Design System (ADS) electromagnetic momentum with GaAS pHEMT 0.1 μm process model. The results shows the proposed method can achieve better input impedance matching and lower NF while the output impedance matching and gain have relatively the same behavior.

A band-selective CMOS low-noise amplifier with current reuse gm boosting technique for 3-5 GHz UWB receivers

The authors have proposed a 3-5 GHz ultra-wideband (UWB) low power and low noise amplifier (LNA) with the TSMC 0.18 μm RF CMOS process, which uses a novel dual input matching network for wideband matching. We have used a current-reuse gm-boosted common-gate topology and shunt-shunt feedback common-source output buffer to improve gain and noise figure with low power dissipation. The proposed dual input matching gm-boosted common-gate LNA has been efficient bandwidth to cover UWB band. It has required less inductors or amplification stages to increase bandwidth as compared with the conventional UWB common-gate LNAs. The broadband input stage has been able to be switched to three frequency bands with capacitive switches. The capacitive switch has replaced a large inductor to resonate at lower frequency band. The band-selective LNA has shown linearity improvement by attenuating the undesired interference of a wideband gain circuit and using less inductors. Simulated performance has shown the gains of 15.9, 17.6, and 16.9 dB, and the noise figures of 3.38, 3.28, and 3.27 dB at the 3.432, 3.960, and 4.488 GHz frequency bands, respectively. The proposed UWB LNA has consumed 5 mW from a 1.8-V power supply.

28 GHz RF Front-End Structure Using CG LNA as a Switch

This letter proposes a compact 28-GHz front-end (FE) structure that uses a common-gate (CG) low-noise amplifier (LNA) as a transmit/receive switch. The power amplifier (PA) output shares a dc bias with the CG LNA input. When the shared dc bias is high, the state of the LNA becomes passive, and the LNA operates as a turned-off shunt switch in the transmitter (TX) mode. The proposed CG LNA switch allows high isolation and linearity with a TX path insertion loss of 0.07 dB at 28 GHz. On the contrary, when the shared dc bias is low, the state of the PA becomes passive and it results in a receiver (RX) path insertion loss of 0.51 dB at 28 GHz. The path losses of the CG LNA switch are minimized by the RF floating bodies of the PA and the CG LNA. This is implemented in a 65-nm CMOS process occupying a 0.215-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> core area. The measured saturation power is 15.3 dBm with 25.1% peak power-added efficiency in the TX mode, and the measured noise figure is 4.9 dB in the RX mode.

A 3–14 GHz, Self-Body Biased Common-Gate UWB LNA for Wireless Applications in 90 nm CMOS

Inspired from continuous growth in the field of low power and low noise wireless communication devices, a low noise amplifier (LNA) using self-body biased common-gate (CG) configuration is presented in this paper. The proposed LNA is designed for 3–14[Formula: see text]GHz ultra-wideband (UWB) frequency range using 90[Formula: see text]nm CMOS process. Common-gate configuration with self-body biasing has been used at the input stage to provide wideband input matching with low noise figure (NF) for the complete UWB frequency. An impedance matching network consisting of parallel to series RLC network has been used between common-gate and cascaded common source (CS) stages. Two stages of the CS configuration have been used for bandwidth enhancement and to increase the power gain (S[Formula: see text]) with acceptable NF. Buffer stage at the output has been used to achieve output reflection coefficient (S[Formula: see text]) less than [Formula: see text]10.8[Formula: see text]dB. The proposed LNA achieves an average S[Formula: see text] of 15.9[Formula: see text][Formula: see text][Formula: see text]0.7[Formula: see text]dB with a maximum of 16.7[Formula: see text]dB at 3.0[Formula: see text]GHz and NF of 1.68–2.7[Formula: see text]dB for 3.1–10.6[Formula: see text]GHz UWB frequency range. It provides input reflection coefficient (S[Formula: see text]) less than [Formula: see text]10.2[Formula: see text]dB, reverse isolation (S[Formula: see text]) less than [Formula: see text]75.8[Formula: see text]dB and a NF of 1.68–4.0[Formula: see text]dB throughout the proposed UWB frequency range. The proposed LNA provides input 1[Formula: see text]dB compression point (P1dB) of [Formula: see text]13[Formula: see text]dBm and input third-order intercept point (IIP3) of [Formula: see text]8[Formula: see text]dBm at 6[Formula: see text]GHz. It consumes 20.1[Formula: see text]mW of power from a 1.2[Formula: see text]V power supply.

A fully integrated 2.4 dB NF capacitive cross coupling CG-LNA for LTE band

This paper presents a common gate low noise amplifier utilizing a passive feedback network that provides a competitive and highly integrated front-end solution for mobile handset devices. This design utilizes a resistive load instead of the inductive one used in other designs to reduce the on-chip silicon area. The design does not need an external matching network which decrease the area of the PCB while achieving a sufficient input impedance matching, S11. It achieves a measured gain higher than 20 dB, noise figure less than 3 dB and input referred third order intercept point (IIP3) value higher than − 2.5 dBm at 2.3 GHz. The design is implemented in 65 nm UMC CMOS technology, occupies a total area of 0.065 mm2 and consumes 5 mW from a 1.4 V supply.

Design of inductively degenerated common source RF CMOS Low Noise Amplifier

The Low Noise Amplifier (LNA) is the first stage in RF CMOS receivers. The Common Gate (CG) LNA and Inductively Degenerated Common Source (CS) LNA are one of the widely used topologies for realizing RF CMOS receivers. The present work emphasizes a simple and exhaustive search procedure for the synthesis and analysis of CMOS CG and Inductively Degenerated CS LNA circuits. The width (W), gate source voltage ( $$ V_{gs} $$ ) and drain source voltage ( $$ V_{ds} $$ ) of the transistors constitute the design space in the circuit design. The design first involves the use of a circuit simulator (HSPICE) to obtain the small signal parameters of the circuit for various W, $$ V_{gs}$$ , and $$ V_{ds} $$ of the transistors and then to generate a Look-Up Table (LUT) for all design points using the obtained values. This LUT is used to meet the target performance specifications along with appropriate analytical expressions derived from the circuit in a numerical simulator (MATLAB). This will enable one to explore the whole design space quickly and fastly for arriving at the optimal values for the device dimensions, bias voltages and bias currents of the two LNA circuits. The design methodology is demonstrated by designing CG and Inductively Degenerated CS LNA circuits using 90 nm CMOS technology library in which Inductively Degenerated CS LNA gets high gain and low noise figure than CG LNA.

A common gate LNA with negative resistance for noise reduction

This paper presents a common-gate (CG) low-noise amplifier (LNA) using a novel negative resistance to improve its noise figure (NF). The new negative-resistance CG-LNA (NR CG-LNA) shows superior performance over the conventional CG-LNAs in terms of power consumption, gain and NF. A prototype designed in 180 nm CMOS technology, occupied a silicon area of 0.57 mm2. The post layout simulations show a maximum gain of 20.2 dB, and a minimum NF of 2.3 dB with 8.5-mW of power consumption operating in 1.95 GHz–2.3 GHz bandwidth, which could be used in Wideband Code- Division Multiple Access (WCDMA) applications.

A sub-mW 2.9-dB noise figure Inductor-less low noise amplifier for wireless sensor network applications

In this paper, a low power differential inductor-less Common Gate Low Noise Amplifier (CG-LNA) is presented for Wireless Sensor Network (WSN) applications. New Shunt feedback is employed with noise cancellation and Dual Capacitive Cross Coupling (DCCC) techniques to improve the performance of common gate structures in terms of gain, Noise Figure (NF) and power consumption. The shunt feedback path boosts the input conductance of the LNA in current reuse scheme. Both shunt feedback and current reuse bring power dissipation down considerably. In addition, the positive feedback is utilized to cancel the thermal noise of the input transistor. The proposed LNA is designed and simulated in 0.18 µm TSMC CMOS technology. Post layout Simulation results indicate a voltage gain of 16.5 dB with −3 dB bandwidth of 100 MHz–3 GHz. Also third order Input Intercept Point (IIP3) is equal to + 1 dBm. The minimum NF is 2.8 dB and the value of NF at 2.4 GHz is 2.9 dB. S11 is better than −13 dB in whole frequency range. The core LNA consumes 985 µW from a 1.8 V DC voltage supply.

Design of Low Power UWB CMOS Low Noise Amplifier using Active Inductor for WLAN Receiver

This paper presents a low power Low Noise Amplifier (LNA) using 0.18µm CMOS technology for ultra wide band (UWB) applications. gm boosting common gate (CG) LNA is designed to improve the noise performance. For the reduction of on chip area, active inductor is employed at the input side of the designed LNA for input impedance matching. The proposed UWB LNA is designed using Advanced Design System (ADS) at UWB frequency of 3.1-10.6 GHz. Simulation results show that the gain of 10.74+ 0.01 dB, noise figure is 4.855 dB, input return loss &lt;-13 dB and 12.5 mW power consumption.

A wideband CMOS single-ended low noise amplifier employing negative resistance technique

A wideband common-gate CMOS low noise amplifier with negative resistance technique is proposed. A novel single-ended negative resistance structure is employed to improve gain and noise of the LNA. The inductor resonating is adopted at the input stage and load stage to meet wideband matching and compensate gain roll-off at higher frequencies. Implemented in a 0.18 [Formula: see text]m CMOS technology, the proposed LNA demonstrates in simulations a maximal gain of 16.4 dB across the 3 dB bandwidth of 0.2–3 GHz. The in-band noise figure of 3.4–4.7 dB is obtained while the IIP3 of 5.3–6.8 dBm and IIP2 of 12.5–17.2 dBm are post-simulated in the designed frequency band. The LNA core consumes a power dissipation of 3.8 mW under a 1.5 V power supply.

Design of Broadband CNFET LNA Based on Extracted I-V Closed-Form Equation

A procedure of extracting a closed-form user-friendly I–V equation for short channel carbon nanotube field-effect transistors (CNFET) in the saturation region is presented by employing a relation between CNFET parameters meeting the experimental results. The methodology is based on the Stanford model and ballistic relation of one channel CNFET. In this regard, the ballistic relation is simplified to a closed-form I–V equation, and then, the parameters are estimated through the fitting algorithm by means of ICCAP and least square method, respectively, and the obtained equation is verified by the experimental results given in the literature. Additionally, an extended quantitative noise analysis is performed at the circuit level and the noise sources implemented in Verilog-A are added to the Stanford CNFET HSPICE model. Subsequently, with the accordance to the extracted I–V equation, a CNFET-based inductor-less broadband common-gate low noise amplifier (LNA) is designed theoretically and its results are confirmed in HSPICE based on the Stanford CNFET model, indicating a proper matching between analysis and simulation. The proposed CNFET-based LNA provides very-high-frequency bandwidth and also lower noise figure in comparison with its contemporary CMOS-based LNA, without any passive spiral inductor.

A Wideband Low-Noise Amplifier with Active and Passive Cross-Coupled Feedbacks

A wideband CMOS common-gate low-noise amplifier (LNA) with high linearity is proposed. The linearity is improved by dual cross-coupled feedback technique. A passive cross-coupled feedback removes the second-order harmonic feedback effect to the input-referred third-order intercept point (IIP3), which is known as one of the limitations for linearity enhancement using feedback. An active cross-coupled feedback, constituted by a voltage combiner and a feedback capacitor is employed to enhance loop gain, and acquire further linearity improvement. An enhanced LC-match input network and forward isolation of active cross-coupled feedback enable the proposed LNA with wideband input matching and flat gain performance. Fabricated in a 0.13 µm RF CMOS process, the LNA achieves a flat voltage gain of 13 dB, an NF of 2.6∼3.8 dB, and an IIP3 of 3.6∼4.9 dBm over a 3 dB bandwidth of 0.1∼1.3 GHz. It consumes only 3.2 mA from a 1.2 V supply and occupies an area of 480×418 um2. In contrast to those of reported wideband LNAs, the proposed LNA has the merit of low power consumption and high linearity.

A +25-dBm IIP3 1.7–2.1-GHz FDD Receiver Front End With Integrated Hybrid Transformer in 28-nm CMOS

A highly linear receiver (RX) front end with integrated hybrid transformer (HT) for frequency-division duplexing mobile communications is reported. The HT, implemented with a three-winding coplanar transformer, is used to interface the RX front end with the antenna and the power amplifier. The primary is driven at its center tap with the transmitted signal and at one input with the antenna signal, while the other input is connected to an on-chip programmable balancing impedance. The two secondary drives a differential push–pull common-gate low-noise amplifier (LNA). Assuming a perfectly linear hybrid only 45 dB of transmitter (TX)–RX isolation and 35 dB of common-mode rejection are required to meet the intermodulation specs thanks to the +25-dBm receiver IIP3. This would drastically simplify hybrid balancing and adaptation loop. Cascaded noise figure of duplexer, LNA, and baseband is below 6.7 dB and TX insertion loss below 4.3 dB from 1.7 to 2.1 GHz. The implemented prototype in 28-nm CMOS has an active area of 0.7 mm2 and requires only 26 mW.