Abstract

This paper presents a common gate low noise amplifier utilizing a passive feedback network that provides a competitive and highly integrated front-end solution for mobile handset devices. This design utilizes a resistive load instead of the inductive one used in other designs to reduce the on-chip silicon area. The design does not need an external matching network which decrease the area of the PCB while achieving a sufficient input impedance matching, S11. It achieves a measured gain higher than 20 dB, noise figure less than 3 dB and input referred third order intercept point (IIP3) value higher than − 2.5 dBm at 2.3 GHz. The design is implemented in 65 nm UMC CMOS technology, occupies a total area of 0.065 mm2 and consumes 5 mW from a 1.4 V supply.

Full Text
Published version (Free)

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call