Common-gate Low-noise Amplifier Research Articles

An Interference-Robust Reconfigurable Receiver With Automatic Frequency-Calibrated LNA in 65-nm CMOS

An interference-robust reconfigurable receiver in 65-nm CMOS is presented. The front end is split into a low-band (LB) RF path (0.1–1.5 GHz) and a high-band (HB) RF path (1–5 GHz). By utilizing a harmonic recombination technique, the LB path could reject the third /fifth-order harmonic interferences. A tunable narrowband dual-feedback common-gate low-noise amplifier (LNA) with $LC$ resonant load provides second-order bandpass filtering to reject the harmonic interferences in the HB path. The RF high-Q bandpass filtering based on the voltage-mode passive mixer and the current-mode low-pass filter in the analog baseband improves the receiver’s resilience to out-of-band interferences. A novel power-detection-based automatic frequency calibration technique is proposed to calibrate the operating frequency of the LNA in the HB path and overcome the effects of process, voltage, and temperature variations. The presented receiver has been implemented in a 65-nm CMOS and consumes 20–76-mW power from 1.2-V power supplies, with a core die area of 5 mm2. The measured results show that the receiver can tolerate −5-dBm interference with 16-dB noise figure (NF) and achieve 95–105-dB maximum conversion gain and 1.7–8-dB NF over 0.1–5 GHz. It also achieves an average harmonic rejection (HR3)/HR5 of 61/68-dB, +7.1/+14.4 dBm in-band/out-of-band input third-order intercept point (OB-IIP3), +71.2-dBm OB-IIP2, and 58.1-dB-image rejection, after the digitally assisted calibrations. The system-level measurements show that the presented receiver achieves 2.1% error vector magnitude (EVM) for 850-MHz Global System for Mobile Communication signals and 5% EVM for band 42 time division duplexing-local thermal equilibrium (LTE) signals, respectively.

A Novel Sub-mW Low-Power gm-boost CMOS Common Gate LNA for Wireless Receiver

A new common-gate (CG) low-noise amplifier (LNA) with a passive gm-boost network (PGBN) is proposed in this work. With a much bigger gm-boost amplification coefficient introduced by the PGBN, the fixed noise reduction coefficient (with the max value to be 1) for the traditional capacitor-cross-coupled CG LNA is broken. As a result, the noise figure (NF) can be further reduced. Moreover, the power consumption can also be greatly reduced simultaneously. The proposed LNA is of great interest for low-power fully integrated wireless communication receiver with relative high NF requirement, which is designed in a TSMC 0.18 μm process. The experimental simulation results show the proposed LNA achieves 7.6 dB power gain, a NF of 1.3 dB, good input/output matching with the S11 and S22 both less than −40 dB, and the IIP3 is measured to be −11.8 dB. The LNA also demonstrate an ultra-low power consumption of 0.67 mW with a 1.8 V power supply, which is quite suitable for “Green” power consumption applications.

A High-Linearity Wideband Common-Gate LNA With a Differential Active Inductor

A capacitor cross-coupled (CCC) wideband common-gate low-noise amplifier (CGLNA) with improved linearity and frequency response is presented. A novel differential active inductor (AI) is designed to improve the in-band gain flatness and high-frequency gain using the gate-inductive gain-peaking technique. The AI prevents the small-signal current flowing to the ground through the gate–drain capacitors. The CCC technique improves noise performance and saves power. However, it will also increase nonlinear distortions due to the boosted signal amplitude. To overcome the CCC-induced linearity deterioration, the derivative superposition technique is employed by using two parallel input transistors biased at different regions. The measurement results of the fabricated prototype in a 0.18- $\mu\text{m}$ CMOS process show that the voltage gain, the minimum noise figure, and the third-order intercept point are 16.9 dB, 2.5 dB, and 5.5 dBm, respectively, within the 3-dB bandwidth from 100 MHz to 1.45 GHz. The CGLNA consumes 9.3 mW from a 1.8-V supply and the active area is $0.29\times 0.26 \text{mm}^{2}$ .

A 5–7 GHz current reuse and gm-boosted common gate low noise amplifier with LC based ESD protection in 32 nm CMOS

Scaling of minimum length of the MOSFET has improved its performance but has reduced the breakdown voltage which makes it prone to Electrostatic Discharge (ESD) damage. This work presents a low-power gm-boosted common gate (CG) ultra wideband (UWB) low noise amplifier (LNA) architecture, operating in the 5---7 GHz range, employing current-reuse technique with LC based Electrostatic Discharge (ESD) protection. Common gate topology supports wide band input matching and noise figure independent of operating frequency. A PMOS common source topology is used as the gm-boosting stage in order to reduce the noise figure and to remove the dependency of noise figure from the bias point. The gm-boosting stage and the amplifier share common bias current to reduce the power consumption of the LNA. A shunt inductor, series capacitor and power clamp are used for protecting the circuit from ESD damage. The ESD circuit is co-designed with the input matching network in order to reduce the area of the layout. The proposed topology has shown significant improvement in gain and noise figure with ESD protection.

An inductorless wideband common-gate LNA with dual capacitor cross-coupled feedback and negative impedance techniques

A wideband common-gate (CG) low-noise amplifier (LNA) with dual capacitor cross-coupled (CCC) feedback and negative impedance techniques is presented for multimode multiband wireless communication applications. Double CCC technique boosts the input transconductance of the LNA, and low power consumption is obtained by using current-reuse technique. Negative impedance technique is employed to alleviate the correlation between the transconductance of the matching transistors and input impedance. Meanwhile, it also allows us to achieve a lower noise figure (NF). Moreover, current bleeding technique is adopted to allow the choice of a larger load resistor without sacrificing the voltage headroom. The proposed architecture achieves low noise, low power and high gain simultaneously without the use of bulky inductors. Simulation results of a 0.18-μm CMOS implementation show that the proposed LNA provides a maximum voltage gain of 25.02dB and a minimum NF of 2.37dB from 0.1 to 2.25GHz. The input-referred third-order intercept point (IIP3) and input 1-dB compression point (IP1dB) are better than –7.8dBm and –19.2dBm, respectively, across the operating bandwidth. The circuit dissipates 3.24mW from 1.8V DC supply with an active area of 0.03mm2.

A linearized common-gate low-noise amplifier using active cross-coupled feedback technique

A wideband linearized common-gate low-noise amplifier (LNA) is proposed. The linearity is improved by active cross-coupled feedback technique. The active cross-coupled feedback circuit, consisting of a complementary source follower and a feedback capacitor, is employed to enhance loop gain, and acquire linearity improvement. A passive cross-coupled feedback removes the second-order harmonic feedback effect to the input-referred third-order intercept point (IIP3). An enhanced LC-match input network and forward isolation of the active cross-coupled feedback enable the proposed LNA with wideband input matching and flat gain performance, respectively. Fabricated in a 0.13 μm RF CMOS process, the LNA achieves a flat voltage gain of 14.5 dB, an NF of 2.5---3.4 dB, and an IIP3 of 3.1---4.3 dBm over a 3 dB bandwidth of 0.1---1.2 GHz. It consumes only 3.5 mA from a 1.2 V supply and occupies an area of 0.2 mm2.

A low power low noise amplifier employing negative feedback and current reuse techniques

This paper presents a low power wideband differential Low Noise Amplifier (LNA) suited for multimode receivers and Wireless Sensor Networks (WSN) in a 0.18μm CMOS technology. By using negative feedback, the stringent trade-off between the input matching and the transconductance (gm) is broken and the required transconductance of input transistor in Common-Gate (CG) LNA is decreased. As a result of this and also using the current reuse implementation scheme, power consumption (PDC) is significantly reduced. The circuit provides high gain and decreased Noise Figure (NF) in spite of low PDC. The LNA structure is fully inductorless, and the core circuit consumes only 1.3mW from a 1.8-V supply occupying an area of 0.032mm2. A maximum voltage gain of 20.1dB is provided with 3dB bandwidth up to 3.3GHz. The input matching is better than −16dB from 20MHz to 3.3GHz. The minimum NF is 3.2dB with third order Input Intercept Point (IIP3) of −2.4dBm.

A linear, low power, 2.5-dB NF LNA for UWB application in a 0.18 μm CMOS

This paper presents an ultra-wideband common-gate low-noise amplifier (UWB CG-LNA) that employs negative feedback to overcome the trade-off that exists between noise and input impedance matching while preserving linearity, stability, and low power operation. The proposed LNA has been designed and simulated via TSMC 0.18-μm CMOS. UWB LNA operates from 3.1 to 10.1GHz. Designed LNA consumes 2.3mA from a 1.8-V supply. Post-layout simulation shows that LNA achieves a maximum voltage gain of 13.7dB, a minimum noise figure of 2.5dB, better than −10dBS11 and +4.5 to +9.5dBm IIP3 across the entire bandwidth. The Volterra series has been used to analyze the linearity of circuit.

A 3–6 GHz Current Reused Noise Canceling Low Noise Amplifier for WLAN and WPAN Applications

A new ultra-wideband common gate low noise amplifier (LNA) for 3---6 GHz WLAN and WPAN applications is presented in which a current reused noise canceling structure utilized in the first stage not only provides a suitable noise performance, but also enhances the linearity characteristics of the LNA in a power efficient manner needed by WLAN/WPAN applications. The overall structure of the proposed LNA, consisting of three stages, namely input matching common gate stage with noise canceling, gain stage, and buffer one, is designed, laid out, and analyzed in 0.18 µm RF CMOS process. The LNA has a noise figure of 3.5---3.6 dB, a high and flat power gain of 20.27 ± 0.13 dB, and input and output losses of better than ?11 and ?14 dB, respectively, over the entire frequency band of 3---5 GHz, while these parameters are 3.5 dB, 20.75 ± 0.25 dB, ?15 and ?9 dB for the frequency band of 5---6 GHz, respectively. IIP2 and IIP3 of the proposed topology are equal to 25.9 and ?1.85 dBm, respectively, at 4 GHz frequency. The proposed LNA has 15.3 mW power dissipation from a 1.8 V supply.

An Inductor-less Sub-mW Low Noise Amplifier for Wireless Sensor Network Applications

This paper presents a Sub-mW differential Common-Gate Low Noise Amplifier (CGLNA) for ZigBee standard. The circuit takes the advantage of shunt feedback and Dual Capacitive Cross Coupling (DCCC) to reduce power consumption and the bandwidth extension capacitors to support 2.4GHz ISM band. An amplifier employing these techniques has been designed and simulated in 0.18µm TSMC CMOS technology. The Simulation results show a gain of 18.2dB, an IIP3 of −4.32dBm and a noise figure of 3.38dB at 2.4GHz. The proposed LNA consumes only 967µW from a 1-V supply.

S-Parameter Comparison of Common Source and Common Gate Low Noise Amplifier

Scattering Parameters or S-parameters are complex numbers which tells us about how voltage waves are propagating in the radio-frequency (RF) environment. In this paper common source and other will be the cascoded common gate topologies have been analyzed. Scattering parameter analysis shows that gain and impedance matching is better for CG LNA. S-parameter is an important tool for LNA design, following information can be obtained a) The frequency b) characteristic impedance (often 50 Ω) c) The allocation of port numbers d)Operating environment such as temperature, control voltage and bias current.

A Wideband Receiver Front-End Employing New Fine RF Gain Control Driven by Frequency-Translated Impedance Property

A new gain control methodology employing frequency-translated (FT) impedance property is proposed for RF amplifiers. By adaptively controlling the baseband impedance through the FT property, fine RF gain control can be achieved without degradation in the RF characteristics such as noise figure (NF), gain, input matching, and bandwidth. To verify the proposed method, a wideband receiver (RX) front-end (FE) with the fine RF gain control has been designed for 2G/3G/4G cellular applications. The implemented RX FE consists of a wideband capacitor cross-coupled common-gate low-noise amplifier, a 25% duty cycle passive mixer with baseband impedance array, a baseband transconductor with variable input capacitance, and a trans-impedance amplifier.

A 2.88 mW <formula formulatype="inline"><tex Notation="TeX">$+$</tex></formula> 9.06 dBm IIP3 Common-Gate LNA With Dual Cross-Coupled Capacitive Feedback

A CMOS common-gate low noise amplifier (LNA) with dual cross coupled capacitive feedback is proposed. The first feedback loop is designed for transcoductance $({\rm g}_{\rm m})$ boosting which is widely known as the cross-coupled common gate (CCCG) topology. The other feedback loop is voltage-current feedback by cross-coupling between the drain node and the source node in the common gate topology. In particular, the first feedback loop is able to reduce the amplification of a second-order signal while it boosts the transconductance of a fundamental signal thus, it can reduce the second order harmonic feedback effect to the input-referred third-order intercept point (IIP3) which is one of the major bottlenecks of linearity enhancement using feedback. As the first feedback removes second-order harmonic distortion, the second feedback successfully enhances IIP3. The proposed LNA achieves excellent performance with low power consumption. The LNA is implemented with a 0.13 $\mu{\rm m}$ CMOS process and measured. The measurement results demonstrate a gain of 18 dB, a noise figure (NF) of 1.94 dB, an IIP3 of 9.06 dBm, an input matching (S11)/output matching (S22) of less than $-$ 10 dB at 900 MHz, and a power consumption of 2.4 mA with 1.2 V supply voltage.

1.8 mW wideband LNA with double capacitor‐cross‐coupled feedback

A 1.8 mW wideband common-gate (CG) low-noise amplifier (LNA) with double capacitor-cross-coupled (CCC) feedback is presented for multiband wireless communication standards. To achieve a low-noise figure (NF) and high-voltage gain under low power consumption, the CG LNA is based on the double CCC feedback and current-reuse techniques. Post-layout simulated results for 0.18 μm CMOS implementations show that the voltage gain is 18.1 dB with a 3 dB bandwidth from 100 MHz to 1.7 GHz and the IIP3 is −4.9 dBm at 1 GHz. The average NF is 2.4 dB within the entire 3 dB bandwidth. The LNA consumes 1.8 mW from a 1.8 V DC supply and the active size is 0.15 × 0.14 mm2.

A 2G/3G/4G SAW-Less Receiver Front-End Adopting Switchable Front-End Architecture

In this paper, a surface acoustic wave (SAW)-less receiver (RX) front-end adopting switchable front-end architecture has been presented for second-generation/third-generation/fourth-generation cellular applications. Depending on the RX-transmitter (TX) frequency separation, a favorable down-mixing architecture is selected between a current-sampling mixer and a voltage-sampling mixer. The proposed switchable architecture meets the specification of an input-referred second-order intercept point (IIP2) for the SAW-less RX while minimizing the power consumption. The implemented RX front-end consists of a wideband capacitor cross-coupled common-gate low-noise amplifier, a 25% duty-cycle passive mixer with IIP2 calibration circuitry, a baseband transconductor, and a trans-impedance amplifier. Fabricated in a 65-nm CMOS process, the SAW-less RX front-end provides conversion gain of 42 dB, and achieves noise figure of below 3.3 dB, out-of-band input-referred third-order intercept point of -2 dBm, and IIP2 of more than 56 dBm. It draws an average current of 14.8 mA from 1.2 V. The die area is 1.71 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A 0.5–2.5 GHz 910 uW complementary LNA employing positive–negative feedback

A 0.5---2.5 GHz ultra low power differential resistive feedback common gate low noise amplifier (RFCGLNA) without the use of inductor is presented. The proposed RFCGLNA adopts the NMOS and PMOS complementary topology to reduce the power consumption by half. Based on common-gate topology, the proposed RFCGLNA employs capacitive cross-coupling (CCC) and resistive feedback techniques. The CCC technique can further reduce the power consumption by half. The resistive feedback technique can constrain the common mode voltages of the proposed RFCGLNA and meanwhile, improve the third-order input intercept point (IIP3). The DC path is supplied by the current source transistor which forms a positive feedback loop to improve the gain at low frequency. Implemented with 65 nm standard complementary metal oxide semiconductor (CMOS) technology, the measured performance achieves 15 dB gain with S11 < ?10 dB in the 0.5---2.5 GHz band. The noise figure (NF) is 3.9---5.0 dB and the IIP3 is 3.1---3.6 dBm. The power consumption is only 910 uW.

A 2.4 GHz Ultra-Low-Power Current-Reuse CG-LNA With Active &lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;${\rm G}_{\rm m}$&lt;/tex&gt; &lt;/formula&gt;-Boosting Technique

An ultra-low-power common-gate low noise amplifier (CG-LNA) for 2.4 GHz wireless sensor network (WSN) applications is proposed in this letter. The current-reuse and active <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$g_{\rm m}$</tex></formula> -boosting techniques are utilized. The analysis, design method and measurement results are shown. An implemented prototype using 0.18 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu$</tex></formula> m CMOS technology is evaluated using on-wafer probing. Measurements also show a gain of 14.7 dB and an <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm IIP}_{3}$</tex> </formula> of 2 dBm at 2.44 GHz. The measured noise figure is 4.8 dB at 2.44 GHz. <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm S}_{11}$</tex></formula> is below <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${-}18$</tex></formula> dB from 2–3 GHz. The proposed LNA consumes 0.58 mW from 1.8 V dc supply.

Minimized Device Junction Leakage Current at Forward-Bias Body and Applications for Low-Voltage Quadruple-Stacked Common-Gate Amplifier

Minimized device junction leakage current at forward-bias body and applications for low-voltage quadruple-stacked common-gate (CG) low-noise amplifier (LNA) is presented in this paper. Diode-connected MOSFETs are proposed to insert between the device bulks and forward bias, resulting in the back-to-back connected diodes and minimized junction leakage current. In addition, interstage matching networks are introduced to the quadruple-stacked CG stages to significantly enhance the small-signal gain of the amplifier. Based on the proposed circuit architectures, the fabricated 0.18-μm complementary metal-oxide-semiconductor LNA can operate at 0.5 V low supply voltage, exhibiting a measured low dc power dissipation of 6.3 mW, high gain of 16 dB, and low noise figure of 5.6 dB at 27.5 GHz. In addition, the theories for analyzing the proposed quadruple-stacked CG amplifier are given in detail, and the mechanisms are validated by experiments.

A gm-boosted common-gate CMOS low-noise amplifier with high P1dB

A 2.4-GHz transconductance (gm)--boosted common gate (CG) low-noise amplifier (LNA) with a high 1-dB compression point (P1dB) is proposed. To overcome the constraint of conventional CG LNA for inpu...

A [formula omitted] dual-band common-gate LNA using active post distortion for mobile WiMAX

This paper proposes an active linearization technique known as Active-Post-Distortion (APD) necessary for high bandwidth applications. The linearization technique is applied to a dual-band cascode Common-Gate (CG) low noise amplifier (LNA) operating in two upper bands of mobile WiMAX. The low frequency cancelation is expressed in power series format and the high frequency analysis using voltera-series explains the effect of tuning load parameters on IIP3. Also voltera-series extract extrema points for tuning load parametric of inductance, capacitance and effective transconductance. In frequency band of 3.5GHz, the LNA attains a noise figure (NF) of less than 3.9dB, input reverse isolation (S11) of less than −15.7dB, input referred third-order intercept point (IIP3) of more than −1.4dBm and power gain of more than 13.2dB. Also the LNA shows a NF of less than 4.2dB, S11 of less than −13.2dB, IIP3 of more than −5.6dBm and power gain of more than 11dB in 5.8GHz of highest frequency band of mobile WiMAX. The results are presented according to a 0.13μm standard CMOS. Using a 1.2V power supply it dissipates 9.36mW.