Common-emitter Stage Research Articles

Variable-Gain Phase Shifter with Phase Compensation Using Varactors

This paper demonstrates a phase compensation technique using varactors for variable-gain phase shifters (VGPSs). The VGPS consists of an I/Q generator and I/Q variable gain amplifiers (I/Q VGAs). I/Q VGAs based on common-emitter stages are enabled to control the gain by adjusting the collector current of the transistor. However, the phase control performance degenerates because the input capacitance varies with the collector current. The proposed phase compensation technique reduces the variation in the insertion phase of the I/Q VGA by adjusting the voltage of the varactor provided at its input and maintaining the input capacitance constant in any gain state. As a result, the VGPS can provide a low phase and amplitude error under phase control. A Ka-band VGPS with the proposed phase compensation technique, fabricated in a 130-nm SiGe BiCMOS process, demonstrates a 0.73° and 0.06 dB improvement in the RMS phase and amplitude error compared with the case without the compensation technique. The VGPS achieves measured RMS amplitude and phase errors of less than 0.19 dB and 0.75°, respectively, in an amplitude control range of more than 20 dB with a frequency range of 28 to 32 GHz.

A +14.2 dBm, 90–140 GHz Wideband Frequency Tripler in 250-nm InP DHBT Technology

A single-chip active frequency tripler circuit with output at F-band (90–140 GHz) is presented. A common-emitter transistor stage with input and output matching circuits is used to produce the third harmonic, followed by a five-pole band-pass filter and a wideband four-stage power amplifier to amplify and increase the output power. The circuit is implemented in a 250-nm InP double-heterostructure bipolar transistor technology with ft/fmax 350/650 GHz, respectively. The chip achieves a peak output power of 14.2 dBm from 99 to 126 GHz at 2-dBm input power and conversion gain of 13 dB at −2-dBm input power. The measured 3-dB output bandwidth is 51 GHz from 90 to 141 GHz which corresponds to 44.2% relative bandwidth. It demonstrates up to 23-dBc rejection ratio of the first and the second harmonics. The dc power consumption is 156 mW at 2-dBm input power. The chip size is $0.9 \times 0.96\,\,\text {mm}^{{2}}$ including pads and achieves a power efficiency of 16.7%.

A Silicon-Based Low-Power Broadband Transimpedance Amplifier

The analysis, design, and implementation of a 50-Gb/s transimpedance amplifier (TIA) in a 0.13- $\mu \text{m}$ SiGe BiCMOS process are presented. The proposed TIA, designed for use in a single-channel optical communication network, is comprised of three stages including: 1) a shunt-peaked, shunt-series feedback stage incorporating a transformer-based positive feedback; 2) an $RC$ -degenerated common-emitter stage; and 3) an inductively degenerated emitter follower. The TIA chip integrates an on-chip 100-fF input capacitor to emulate the photo-detector junction capacitor, and achieves a measured transimpedance gain of 41 dB $\Omega $ and an input-referred current-noise spectral density of 39.8 pA/ $\sqrt {Hz}$ over a 50-GHz bandwidth. The TIA achieves an open eye at 50 Gbps with random jitter of 2.3-ps rms (including the jitter contribution of the test fixture). The prototype chip occupies 0.58 mm2 (including pads) of die area and dissipates 24 mW of dc power from a 2-V supply voltage (i.e., less than 0.5 pJ/bit).

Mathematical Modelling of the LC-Ladder and Capacitive Shunt-Shunt Feedback LNA Topology

In this paper a new low noise amplifier configuration is proposed to achieve wideband operation. This configuration consists of an LC-ladder filter and a common-emitter stage employing shunt-shunt capacitive feedback to realize wideband matching. Design equations for this configuration are derived, as well as equations for the important performance measures namely noise figure, gain and IIP3. The results of a design for achieving typical low noise amplifier specifications in the ultra-wideband are calculated from these equations and plotted. Without any optimization S11 of less than -10 dB over the entire frequency band and a minimum noise figure of 2.7 dB are predicted when achieving S21 of 20 dB. These results indicate that very good performance can be attained through the use of this technique. Simulations were also done to verify the calculated results.

A Methodology for Fast VSWR Protection Implemented in a Monolithic 3-W 55% PAE RF CMOS Power Amplifier

In this paper, the protection of CMOS power amplifiers against load mismatch is addressed. To this purpose, a closed-loop protection circuit is proposed, which is based on a novel current-mode detection and comparison technique. The circuit allows a faster protection lock-in, by enabling peak detection and loop frequency compensation to be performed at the same circuit node, thus reducing the number of low-frequency poles and improving loop bandwidth. The effectiveness of the method is demonstrated through the implementation of a monolithic 0.25-mum 2-V CMOS power amplifier for GSM applications, which can deliver a 3-W output power with 55% overall PAE. The amplifier is able to sustain a 20:1 load VSWR at full power. Excellent RF performance and VSWR ruggedness are hence attained simultaneously, despite a simple common-emitter power stage is used. An experimental reliability assessment allowed the cognizant choice of the maximum drain-gate stress that could be tolerated. Device degradation was characterized by operating a power gain cell at RF, under real-world load and power conditions. Analysis of the degradation data enabled the design of an efficient, yet provably reliable, power amplifier.

Novel cross-connected cascode differential amplifier

We report on a novel amplifier circuit–differential cross-connected cascode1. Its fundamental distinction from an ordinary differential cascode lies in simultaneous feeding of input signal both to the common emitter (source) and common base (gate) stages, which are cross-connected. Such a connection results in the creation of two loops of positive current feedback. The stability of the amplifier is achieved due to low gain and phase shift in the loops. We show that the input signal is amplified in the input circuit. The input and output impedances are gained significantly as well. The current gain is increased considerably and the bandwidth is essentially expanded. Simulation results of such a cascode designed with IBM BJT sige5am and CMOS bicmos7hp transistors are presented. When compared with the ordinary cascode, the predicted and actually obtained bandwidths proved to be more than twice as wide: 8.6–18.7 GHz and 3.4–8.7 GHz on BJT and CMOS based, respectively.

Notice of Violation of IEEE Publication Principles A 54 dBOmega + 42 dB 10 Gb/s SiGe transimpedance-limiting amplifier using bootstrap photodiode capacitance neutralization and vertical threshold adjustment

A high-gain 10 Gb/s transimpedance-limiting amplifier (TIA-LA) capable of directly driving a SERDES IC was realized in a 60 GHz fT 0.2 mum SiGe BiCMOS SOI process. The shunt-feedback common-emitter input stage uses a bootstrap technique to neutralize the photodiode parasitic capacitance. Cascode configurations and cross-coupled Miller capacitance cancellation were used to minimize the input capacitance of the signal path stages. This reduces the number of inter-stage isolation emitter- followers, allowing low-voltage operation. A signal-amplitude-dependent adjustable threshold was implemented in the back-end limiting stages by using inverse hyperbolic tangent circuits. Integrating the high-gain TIA-LA signal path on the same die was made possible by using an SOI process in conjunction with die thinning to reduce substrate coupling and minimizing the output-to- input bondwire magnetic coupling through a careful pin location selection. The main limiting-TIA IC specifications include: 96 dBOmega total gain given by 54 dBOmega TIA gain and 42 dB LA voltage gain, 12 muA input sensitivity, < 8 pA/ radicHz input equivalent noise, 0.3 W power consumption from a 3.3 V supply and 1.8 times 1.8 mm2 die area.

2-Terminal floating bandgap voltage reference

A circuit is described for a 2-terminal bandgap voltage reference that is functionally equivalent to a very-low-impedance low-noise 1.2 V Zener diode. The circuit is all-npn, it is simple (it closely resembles five common-emitter stages connected in cascade), yet it is fully compensated for base-current and collector-voltage variations. Being 2-terminal, the circuit can be floated to provide a constant voltage difference between any two nodes in an integrated circuit.

A SiGe BiCMOS transmitter module for IMT2000 applications

This paper describes a Tx module for IMT2000 applications consisting of an up-conversion mixer and a variable-gain driver amplifier. The up-conversion mixer, based on the Gilbert active topology has a power gain of 4.8 dB and consumes 15-mA current from a 3-V supply. The variable-gain driver amplifier comprises a gain-controlled stage of the current steering structure and a common emitter stage, and has a variable-gain range of over 30 dB with 30.3-mA current consumption. The Tx module achieves a gain error of less than 1.2 dB over a 30-dB gain range, an output IP3 of 25 dBm, and an output PI dB of 7.4 dBm at the maximum gain of 24.5 dB. It occupies 1.0 /spl times/ 1.2 mm.

Intermodulation Distortion of a Bipolar Common-Emitter Amplifier With Arbitrary Emitter Impedance and Input Matching Network

In this paper, concise formulas for the intermodulation distortion of a bipolar common-emitter amplifier stage with arbitrary emitter impedance and input matching network are presented. These expressions provide quantitative insight in the influence of transistor properties, emitter degeneration and input power matching on distortion. Only a small set of measurable transistor parameters is needed. As examples, IIP3 is calculated for transistor only, transistor with emitter inductance, and transistor with emitter inductance and input matching circuit. Two transistors are compared: a double-poly Si transistor and a SiGe transistor in a similar process. A good agreement between analytical and numerical results is obtained.

High-frequency analysis of linearity improvement technique of common-emitter transconductance stage using a low-frequency-trap network

It is well known that a low-frequency-trap network can be added to the base of an inductively-degenerated common-emitter transconductance stage to improve its third-order intercept point, but not its 1-dB compression point. High-frequency equations in Volterra series are used to explain this phenomenon. Analytical and experimental results show that the third-order intercept point increases with the capacitance within the low-frequency-trap network.

High-frequency nonlinearity analysis of common-emitter and differential-pair transconductance stages

Equations describing the high-frequency nonlinear behavior of common-emitter and differential-pair transconductance stages are derived. The equations show that transconductance stages using inductive degeneration are more linear than those using capacitive or resistive degeneration, and that the common-emitter transconductance stages are more linear than the differential-pair transconductance stages with the same bias current and transconductance. The nonlinearity equations can also be used to explain the class AB behavior of the common-emitter transconductance stage with inductive degeneration.

A class AB monolithic mixer for 900-MHz applications

A class AB downconversion mixer for 900-MHz applications is presented. The circuit is implemented in a 25-GHz f/sub T/ bipolar process and consumes 10.2 mA total current from a 3-V supply. The design has a power gain of 7.5 dB and operates with supply voltages from 2.7 to 5 V. A single-sideband noise figure of 7.5 dB is achieved by design simplicity, use of bond-wire degeneration in the common-emitter driver stage, and optimization of the device sizes and bias currents. An input 1-dB compression point of -1.5 dBm is achieved by exploiting the class AB behavior of the common-emitter driver stage.

Integrated high frequency low-noise current-mode optical transimpedance preamplifiers: theory and practice

Classical designs of optical transimpedance amplifiers for p-i-n photodiode receiver circuits generally employ common-emitter or common-source input stages. In this paper we explore the design of a new class of low noise current-mode optical transimpedance preamplifier based upon common-base input stages. Simulated and measured results of a 10 GHz GaAs HBT and 3.5 GHz BiCMOS common-base input optical transimpedance amplifier are presented. >

On the design of low-noise current-mode optical preamplifiers

Classical designs of optical transimpedance amplifiers for p-i-n photodiode receiver circuits generally employ common-emitter or common-source input stages. In this paper we explore the design of a new class of low-noise “current-mode” optical preamplifier based upon common-base and common-gate input stages. Two current-mode designs are considered, firstly an improved bipolar common-base configuration and secondly a GaAs MESFET common-gate configuration. Both designs employ current-feedback techniques to achieve higher transimpedance gains than is obtained with classical voltage-feedback structures for the same operating bandwidth. A theoretical noise analysis of the new current-mode designs confirms the expected low noise performance. Finally, experimental noise measurements at 100-MHz bandwidth indicates that under certain conditions electrical noise improvements of up to 4 dBs over classical designs can be obtained with the new current-mode circuits.

Improved bipolar transistor performance in CMOS by novel use of parasitic collector resistance

A design and layout technique which allows the use of the parasitic bipolar collector resistance as a load component in common emitter stages is discussed. This is achieved by using an extra collector contact in a force-sense arrangement. This removes the need for another load component, thereby reducing area, but more importantly the parasitic collector resistance is no longer limiting the transistor speed. The principle of operation is verified with fabricated transistors. The technique is applied to a bipolar/CMOS analog voltage comparator, and a speed improvement of a factor of three is obtained over a previous design in the same process which does not employ this technique. Simulation results for a voltage comparator designed by the technique, which resolved 12 b in 40 ns, are presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Transimpedance optical preamplifier with a very low input resistance

A PIN photodiode-bipolar transistor transimpedance optical preamplifier with a very low input resistance is described that exhibits certain advantages over more conventional designs using common-emitter or common-collector input stages. The common-base input configuration enables optimum performance to be maintained with lower-cost photodiodes exhibiting a moderate capacitance of 2-7 pF.

Graphical techniques for the study of biasing in common-emitter amplifiers

Abstract The role of symmetrical swing and voltage gain specifications in the design of a common-emitter amplifier stage which is required to have acceptable performance over a given temperature range is considered. It is shown that a hierarchical approach, wherein the original problem is converted into one of coordinating the solutions to a set of appropriately structured subproblems, leads to a set of graphical representations which are quite useful in depicting the constraints of this design problem. A design procedure and some interesting bounds on the attainable specifications arc developed from these results and are illustrated via two design examples.

Switching Time of a Transistor with Tunnel Diode Coupling

The analysis of the switching action of a tunnel diode is extended to include the effects of the collector transition region capacitance which arise when a tunnel diode is driven from a common-emitter transistor stage. A piece-wise linear analysis is used which predicts the collector voltage waveform and switching times with good accuracy. The turn-off time constant is shown to be related to the transient current gain <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">\delta_0 = \frac {\alpha_0(C_L + C_{TC})} {(1-\alpha_0)C_L + C_{TC} }</tex> rather than directly to the static current gains <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">\alpha_0</tex> or <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">\alpha_0/( 1 - \alpha_0 )</tex>

Amplifiers using bipolar and unipolar transistors with limited drain—source voltage

An important class of amplifiers uses a field-effect device in the first stage and a bipolar transistor in the second. If the drain-source voltage of the former is limited to the base-emitter voltage of the latter, a particularly simple circuit arrangement results. Other advantages of operation in this mode include reduction in the power dissipated in the field-effect device, improvement in high-frequency response and, when circuit constants are suitably chosen, some degree of inherent compensation for change of working conditions due to thermal effects. Of the four possible configurations which give high input impedance and voltage gain, it is shown that only two can easily be stabilised against working-point changes, and of these one [in which a common-drain (c.d.) amplifier precedes a common-emitter (c.e.) stage] is preferred, because it exhibits higher gain and lower output impedance and needs only a single polarity of supply voltage. The transfer conductance, input and output impedances and thermal drift of the c.d.-c.e. amplifier are calculated, using an equivalent circuit in which the drain-source channel is represented by a variable resistor.