Commercial CAD Tools Research Articles

Static IRdrop Analysis Using Open Source CAD Software

This paper investigates the open source static IRdrop analysis tool, PDNSim, which is part of the OpenROAD computer-aided design tool. The main approach used for static IRdrop analysis is discussed, namely the compilation of an equivalent circuit model used for further calculations. The results of static IRdrop analysis obtained using PDNSim are compared with the results obtained using modern commercial CAD tool and the error of the obtained analysis results is evaluated.

Design and Characterization of a Novel FinFET based NCL Cell Library for High Performance Asynchronous Circuits

In recent times, synchronous circuits are facing design related issues like clock skew, glitch power, EMI, leakage power, etc. The clock-less design paradigm – Asynchronous design challenges most of these issues and accepted as a better alternative to clocked circuits. QDI based Null Convention Logic (NCL) is such a clock-less design concept. However, NCL designs couldn’t get wide spread acceptance due to unavailability of commercial CAD tools and design compatible NCL standard cell library. The proposed research work in this paper demonstrates design and characterization of FinFET based NCL cell library to facilitate QDI based asynchronous circuit design. The NCL cells are designed with ASAP 7nm PDK. A complete set of 27 NCL threshold gates are developed and characterized in cadence using ocean scripting. Various time and energy models are extracted for different process corners using EDA platform. The proposed work will help research scholars to implement NCL based asynchronous circuits. This paper also demonstrates comparative performance analysis of bulk-CMOS and multi-gate FinFET based NCL threshold gates in 16 nanometer technology. The analysis has concluded average 19% of improvement in power-delay produce for FinFET based cells compared to its CMOS counterparts. To showcase two-dimensional comparison, various static and semi-static NCL gate structures are also compared in term of their power and speed. Various arithmetic circuits are designed using these standard NCL cells to demonstrate its application. The results indicated substantial performance improvement in terms of power and speed.

A survey of ASER members on artificial intelligence in emergency radiology: trends, perceptions, and expectations.

There is a growing body of diagnostic performance studies for emergency radiology-related artificial intelligence/machine learning (AI/ML) tools; however, little is known about user preferences, concerns, experiences, expectations, and the degree of penetration of AI tools in emergency radiology. Our aim is to conduct a survey of the current trends, perceptions, and expectations regarding AI among American Society of Emergency Radiology (ASER) members. An anonymous and voluntary online survey questionnaire was e-mailed to all ASER members, followed by two reminder e-mails. A descriptive analysis of the data was conducted, and results summarized. A total of 113 members responded (response rate 12%). The majority were attending radiologists (90%) with greater than 10years' experience (80%) and from an academic practice (65%). Most (55%) reported use of commercial AI CAD tools in their practice. Workflow prioritization based on pathology detection, injury or disease severity grading and classification, quantitative visualization, and auto-population of structured reports were identified as high-value tasks. Respondents overwhelmingly indicated a need for explainable and verifiable tools (87%) and the need for transparency in the development process (80%). Most respondents did not feel that AI would reduce the need for emergency radiologists in the next two decades (72%) or diminish interest in fellowship programs (58%). Negative perceptions pertained to potential for automation bias (23%), over-diagnosis (16%), poor generalizability (15%), negative impact on training (11%), and impediments to workflow (10%). ASER member respondents are in general optimistic about the impact of AI in the practice of emergency radiology and its impact on the popularity of emergency radiology as a subspecialty. The majority expect to see transparent and explainable AI models with the radiologist as the decision-maker.

Impact of place and route strategy on FPGA electromagnetic emission

As technology scales down, dense integration and high operating frequencies associated with increased number of I/O buffers are factors contributing to electromagnetic emission (EME) increase of FPGA devices. Noting that the EME depends not only on the dynamic power dissipated by the device, but also on the coupling degree between the layout of the routed tracks and the signal switching activity along with these tracks, it is of high interest and challenging to investigate FPGA EME performance. With this purpose, this paper presents an analysis about the impact of the placement and routing (P&R) process of logic inside the FPGA on the chip EME level. With this goal in mind, a softcore processor was placed and routed based on three different strategies in the configurable logic block (CLB) array of a commercial FPGA and executed an application code running over an operating system (OS). One of these P&R strategies is performed automatically by a commercial CAD tool, whose results are compared against the other two manually P&R processes of the FPGA. Two experiments have been performed. The obtained results indicate that the EME level can be affected up to 21.8% by the way the processor is placed and routed inside the FPGA. In this scenario, we suggest to improve the efficiency of the commercial CAD tool to execute the P&R process by having in mind the FPGA EME.

Uniform Illumination for Nonplanar Surface Based on Freeform Surfaces

The shapes of target surfaces are nonplanar on many occasions such as undulating road and roof of the tunnel, while the lighting quality generated by traditional nonimaging optical lenses still needs to be further improved. As a result, a novel method is proposed for the design of optical elements generating uniform irradiance distribution on nonplanar target surfaces. A matrix is introduced instead of a single height parameter for improving the mathematical model of asymmetrical lenses, hence a modified mathematical model based on single LED chip and desired irradiance distribution of the nonplanar target surface is established. By solving the equations with the iterative method, the asymmetrical lenses can be obtained through commercial CAD tools. Three different nonplanar surfaces are used to verify the validity of the proposed method, including an inner-spherical surface, undulating surface and arched surface. The results show that the illumination uniformity of the target surface can reach over 70%, and the light efficiency is more than 83%, which are much better than that generated by traditional methods.

Synthesizable Memory Arrays Based on Logic Gates for Subthreshold Operation in IoT

This paper identifies novel directions of standard-cell-based synthesizable memory design. A compact 18T-bitcell of OR-AND-Invert (OAI) and AND-OR-Invert (AOI) logic gates is presented with bit-selective write and multiplexed read accesses. It reduces the bitcell area by 11%–40% compared to the state-of-the-art clock-gating-based D-latch schemes while avoiding custom-cell design. The improved storage density comes from the tight integration on two levels–coupling the read multiplexing within each bitcell and taking advantage of structured datapath placement in bitcell arrays by using commercial CAD tools. As measured on a 40 nm SRAM of 90 kb, the OAI/AOI-gate-based synthesizable memory features 0.4 V minimum access voltage, 30 fJ minimum read energy per bit, and a leakage power of 1.4 pW per bit at 0.3 V data retention voltage. It is ideally suited for IoT-node design operating in sub- $V_{\mathrm {t}}$ for joint dynamic energy and leakage power reduction. Further, it enables fast turn-around times by IP reuse over technology nodes with minimal (re)design effort.

Design Flow Methodology for Radiation Hardened by Design CMOS Enclosed-Layout-Transistor-Based Standard-Cell Library

Ionizing radiation degrades the electrical characteristics of MOS devices, reducing their reliability, performance, and lifetime; therefore, hardening techniques are required for the proper functioning of those devices when exposed to harsh environments. Nonetheless, in the context of design flow automation, necessary to synthesize complex digital circuits, there is a lack of reliable foundry-provided Radiation Hardening by Design (RHBD) cell libraries. In this work, a complete RHBD flow methodology employing enclosed-layout transistors (ELTs) and guard rings, transparent to the designer, and fully compatible with commercial CAD tools and standard fabrication processes is presented. The proposed flow includes the automated calculation of the effective aspect ratio of the ELTs for annular and rectangular topologies, and a template proposal for digital cells, as well as series and parallel arrangements. Moreover, calculation of aspect ratio between pull-up and down networks and output buffers sizing using Logical Effort (LE) methodology, i.e., timing optimization accounting for typical commercial digital design constraints, is considered. Test structures, enclosing single n,pMOS devices, series and parallel arrangements, inverter cells, ring oscillators, and output buffers, were fabricated in two different technology nodes (600 nm and 180 nm). The experimental results were compared to SPICE simulations performed using the models here implemented. The results indicate that the flow methodology is feasible to implement and fully compatible with the CAD tools employed for circuit design. Besides, two case studies were first silicon-proven, presenting fully functional behavior under typical conditions.

A high performance dual clock elastic FIFO network interface for GALS NoC

A dual clock register based elastic First-In First-Out Architecture is presented for Globally Asynchronous Locally Synchronous (GALS) Network on Chip interface. The FIFO is designed using synchronous elastic methods, facilitating its synthesis with commercial CAD tools. This FIFO supports arbitrary phase and frequency for read and write operations and prepares safe data transmission between different clock domains. The presented structure can be easily used as an interface between synchronous or asynchronous GALS modules. The FIFO is simulated and analyzed with 32 nm PTM library in HSPICE. Metastability, process variation, throughput, power, area, delay and maximum frequency are analyzed. Results show elastic FIFO power delay product (PDP) is 23% less than similar synchronous FIFOs. Our proposed elastic FIFO has double capacity while the area is almost the same. The elastic FIFO tolerates better high variability and can preserve its functionality by 5% in average more than the DSPIN synchronous FIFO in presence of variation.

A comprehensive study of cryogenic cooled millimeter-wave frequency multipliers based on GaAs Schottky-barrier varactors

AbstractThe benefit of cryogenic cooling on the performance of millimeter-wave GaAs Schottky-barrier varactor-based frequency multipliers has been studied. For this purpose, a dedicated compact model of a GaAs Schottky-barrier varactor using a triple-anode diode stack has been developed for use with a commercial RF and microwave CAD tool. The model implements critical physical phenomena such as thermionic-field emission current transport at cryogenic temperatures, temperature dependent mobility, reverse breakdown, self-heating, and high-field velocity saturation effects. A parallel conduction model is employed in order to include the effect of barrier inhomogeneities which is known to cause deviation from the expected I--V characteristics at cryogenic temperatures. The developed model is shown to accurately fit the I--V --T dataset from 25 to 295 K measured on the varactor diode stack. Harmonic balance simulations using the model are used to predict the efficiency of a millimeter-wave balanced doubler from room to cryogenic temperatures. The estimation is verified experimentally using a 188 GHz balanced doubler cooled down to 77 K. The model has been further verified down to 14 K using a 78 GHz balanced doubler.

Forward Scatter Radar for Air Surveillance: Characterizing the Target-Receiver Transition from Far-Field to Near-Field Regions

A generalized electromagnetic model is presented in order to predict the response of forward scatter radar (FSR) systems for air-target surveillance applications in both far-field and near-field conditions. The relevant scattering problem is tackled by developing the Helmholtz–Kirchhoff formula and Babinet’s principle to express the scattered and the total fields in typical FSR configurations. To fix the distinctive features of this class of problems, our approach is applied here to metallic targets with canonical rectangular shapes illuminated by a plane wave, but the model can straightforwardly be used to account for more general scenarios. By exploiting suitable approximations, a simple analytical formulation is derived allowing us to efficiently describe the characteristics of the FSR response for a target transitioning with respect to the receiver from far-field to near-field regions. The effects of different target electrical sizes and detection distances on the received signal, as well as the impact of the trajectory of the moving object, are evaluated and discussed. All of the results are shown in terms of quantities normalized to the wavelength and can be generalized to different configurations once the carrier frequency of the FSR system is set. The range of validity of the proposed closed-form approach has been checked by means of numerical analyses, involving comparisons also with a customized implementation of a full-wave commercial CAD tool. The outcomes of this study can pave the way for significant extensions on the applicability of the FSR technique.

A procedure for the extraction of a nonlinear microwave GaN FET model

SummaryIn this paper, we describe an extraction procedure of nonlinear models for microwave field‐effect transistor (FET). We use a nonlinear model available in commercial CAD tools, and we extract the parameters by combining direct extraction and numerical optimization. We determine a first estimate of the model parameters by few DC and S‐parameter measurements. Next, we refine the parameters by optimization against low‐frequency and high‐frequency vector‐calibrated large‐signal measurements gathered with a Large‐Signal‐Network Analyzer (LSNA). As case study we consider a 0.25 × 200 µm2 GaN FET on SiC for power amplifier applications. Ultimately, we want to show that a good accuracy level can be achieved while minimizing the extraction effort and that an accurate model can be built and suitably tailored depending on the final application. Copyright © 2016 John Wiley & Sons, Ltd.

An affordance-integrated approach for design knowledge reuse

Design knowledge reuse is regarded as an effective strategy for design organizations to develop products with shorter time and less effort. However, existing design reuse approaches primarily focus on reusing the geometrical information of similar parts, with a wealth of contextual knowledge behind detailed design results lost. This paper presents an affordance-integrated approach for the reuse of detailed design knowledge, which can be employed to help designers determine the values of geometrical design parameters. First, this paper introduces an affordance-integrated model, called the structure-behavior-affordance, to represent the detailed design information. Then an affordance-based approach is proposed to help designers reuse the detailed design knowledge, which is also integrated with commercial CAD tools. Finally, the proposed approach is implemented as a detailed design knowledge reuse system and a turbocharger shell fixture is adopted as an example to illustrate the proposed design knowledge reuse approach.

Millimeter Wave Characterization of Wire Bond Transitions for W-Band Electromagnetic Sensor

This paper presents millimeter wave characterization and models of various wire bond transitions between chip’s ground-signal-ground pad (GSG) and microstrip (MS), include single-wire-nomatch MS-GSG transition, double-wire-nomatch MS-GSG, single-wire-match MS-GSG transition, and double-wire-match MS-GSG transition. It also presents the 3D full-wave electromagnetic simulation. Analysis results show that the double-wire-match MS-GSG transition’s characteristic is better than other three transitions in the whole W band. The accurate extracted parameter values are used for the lumped equivalent circuit model, whose simulation results are good with the full wave simulation results. The error between lumped equivalent circuit and full-wave models is of the order of ±0.2dB for S11 and S21 in the frequency range 75 - 105GHz. The proposed lumped equivalent circuit is suitable to be implemented in commercial microwave CAD tools for the electromagnetic sensor designing.

A closed‐form equation approach to multi‐port/multi‐zone behavioral modeling of GaN FET Amplifiers

SummaryIn this paper, a systematic method for the simulation of weakly and mildly nonlinear GaN FET amplifiers is reported. The core of the proposal is a third‐order Volterra‐based behavioral model with multi‐spectral and multi‐node capabilities that is formally derived from a circuit‐level representation. Starting with the equivalent circuit of a typical FET device with thermal power feedback and fading memory, described in terms of its large‐signal functions, closed‐form expressions for the kernels at the gate, drain and thermal nodes are developed up to the third order. The use of these kernels allows the calculation of the responses in the dc, first‐, second‐ and third‐harmonic zones, which are shown to be dependent on the frequency response of the amplifier circuit terminating impedances and thermal filter. The simulation approach has been applied to calculate the nonlinear response of a typical power amplifier circuit, showing the ability of the proposed approach to provide an accurate prediction of multi‐spectral, multi‐node, multi‐bias characteristics, including AM/AM‐AM/PM conversion, spectral regrowth, intermodulation, and temperature rise, under diverse input signal waveforms and bandwidths. These results have been successfully compared with commercial CAD tools based on harmonic balance or envelope simulation. Copyright © 2014 John Wiley & Sons, Ltd.

Small-Versus Large-Signal Extraction of Charge Models of Microwave FETs

In this letter we extract the parameters of the charge equations of a microwave transistor nonlinear model which is available in commercial CAD tools. In particular, the charge model parameters are extracted starting from small- and large-signal measurements. A better accuracy can be achieved when using large-signal measurements since the model parameters are obtained from experimental data which better reproduce the actual operating condition of the device under test. An advanced $0.15\times 300 \mu{\rm m}^{2}$ pHEMT in GaAs technology, aimed at cold-FET mixer design, is considered as case study.

Transient‐based conversion matrix approach for nonlinear stability analysis

A new methodology aimed at assessing the large-signal stability of nonlinear driven circuits in the large-signal regime is presented. The procedure combines the conversion matrix approach with a transient envelope simulation and can be implemented with most commercial nonlinear microwave CAD tools. A method for the analysis of the onset of spurious oscillation in nonlinear circuits operating in large-signal conditions is also given and criteria for the evaluation and modification of the critical loads that give rise to spurious frequencies are provided. This approach has been successfully tested on a medium-power amplifier.

Modeling Terahertz Plasmonic Si FETs With SPICE

As operating frequencies of Si FETs continue to grow, commercial circuit modeling tools must provide accurate simulations at very high frequencies with the ability to model plasmonic FETs in large and complex circuits. Traditional compact SPICE models used by commercial CAD tools model the channel resistance and capacitance and gate resistance as single lumped elements or use approximations to model the distributed nature of the FET channel. At high frequencies, these models become inaccurate and fail to model device physics properly. To describe plasmonic FETs, a THz SPICE model is developed for Si FETs. The THz SPICE model is validated experimentally to be in close agreement with measured results. The model is used to show predicted device response at different technology nodes.

The Effect of Random Dopant Fluctuations on Logic Timing at Low Voltage

In order to achieve ultra-low power (ULP), ICs are being designed for V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> ≤ 0.5 V. At these low voltages, random dopant fluctuations (RDFs) result in a stochastic component of logic delay that can be comparable to the global corner delay. Moreover, the probability density function (PDF) of this stochastic delay can be highly non-Gaussian. In order to predict the statistical impact of RDF-induced local variations on logic timing, it is necessary to incorporate these effects into a timing closure methodology. This paper presents a computationally efficient methodology for stochastic characterization of standard cell li- braries at low voltage, where the cell delay is a nonlinear function of the transistor random variables (RVs), and the resulting cell delay has a non-Gaussian PDF. It also presents a computation- ally efficient methodology for computing any point on the PDF of a timing path (TP) delay, in the case where cell delays are non-Gaussian. The method is called nonlinear operating point analysis of local variation (NLOPALV). The general NLOPALV theory is developed. It is applied to cell library characterization, and the accuracy of the NLOPALV approach is validated by comparison to Monte Carlo simulation. NLOPALV is also applied to timing path analysis on a 28 nm DSP IC. The approach has been implemented using commercial CAD tools, and integrated into a commercial IC design flow. The NLOPALV approach gives timing results that are within 5% accuracy compared to Monte Carlo analysis at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> = 0.5 V. This compares to errors on the order of 50% when the Gaussian approximation is used.

Modeling Techniques of Nested Helical Structure Based Geometry for Numerical Analysis

The aim of this paper is to introduce a new methodology of defining and modeling the nested helical structure (NHS) for wire ropes, and to present an accurate wire rope 3D solid modeling, which can be used for finite element analysis. Both single and nested helical wire parametric equations are presented. Derivation of the Frenet-Serret frame for the helical structures is explained, which enables one to define a normal plane along the centerline of a single helical or nested helical curve in 3D space. Both single helical and nested helical solid structures are generated by sweeping a circle or a quadrilateral by using the moving trihedron along the centerline of the helical geometry. When the length of the NHS is increased, surface quality of the NHS diminishes rapidly and it is not possible to generate a good mesh by using the commercial CAD tools. However, the proposed method introduces a solution of modeling helical structures without length limitation with generating an accurate and valid mesh. Illustrative examples are presented to show the benefits of the proposed modeling procedure by using finite element analysis.

General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space

In this paper, a general and complete design flow for nanometer flip-flops (FFs) is presented. The proposed design methodology permits to optimize FFs under constraints within the energy-delay space through extensive adoption of the Logical Effort method, which also allows for defining the bounds in the design space search. Transistors sizing is rigorously discussed by referring to cases that occur in practical designs. Appropriate metrics with clear physical meaning are proposed and various interesting properties are derived from circuit analysis. A well-defined design procedure is derived that can be easily automated with commercial CAD tools. In contrast to previous works, the impact of local interconnections is explicitly accounted for in the design loop, as is required in nanometer CMOS technologies. A case study is discussed in detail to exemplify the application of the proposed methodology. Extensive simulations for a typical FF in a 65-nm CMOS technology are presented to show the whole design procedure and validate the underlying assumptions.