Commercial CAD Tools Research Articles

Feature-based spline optimization in CAD

In this paper, an advanced method for CAD-based spline structure optimization is investigated. The method is based on the combination of the commonly known parameter-based spline shape optimization and a recently presented feature-based structure variation concept for commercial CAD tools. The aim is to extend common parameter-based spline shape variation by the additional possibility to automatically add and remove control points or entire splines directly in CAD space. Such advanced spline modification provides a new level of flexibility in general geometry-based structural optimization. Using these splines to build CAD models, entirely new structures may be automatically generated during an optimization run through this newly gained flexibility in spline manipulation. The idea is to roughly define a continuous design space by basic splines and to gradually increase their shape complexity by control point number variation during optimization. Thus, operating on a knowledge-lean initialization—a design space bounded by basic splines and filled with material—this combination further extends the search and solution spaces of CAD-based structural optimization. The paper provides an outlook towards automated geometry-based structure creation combining nowadays commercial CAD software and a dedicated variation and optimization framework for geometry-based structural optimization.

On the Large Signal Evaluation and Modeling of GaN FET

The large signal performance and model for GaN FET devices was evaluated with DC, S-parameters, and large signal measurements. The large signal model was extended with bias and temperature dependence of access resistances, modified capacitance and charge equations, as well as breakdown models. The model was implemented in a commercial CAD tool and exhibits good overall accuracy.

On the device design assessment of multigate FETs (MuGFETs) using full process and device simulation with 3D TCAD

A design evaluation is reported for multigate FETs (MuGFETs) by implementing a full process flow using a commercial three-dimensional technology CAD (TCAD) tool within the context of optimizing the device design and underlying fabrication processes. The simulation is based on and refers to the development of the SOI-based 30nm MuGFET devices. Using our real process flow, various process simulation parameters from diffusion and activation models are first calibrated to the experimental data. Device simulations are then performed with varying fin doping, fin width, fin height, Ldd and halo implant tilt, and box thickness. For a given fin thickness and increasing fin height, the threshold voltage, off-current, delay and short channel effects (SCEs) remain approximately insensitive, while the on-current and transconductance increases approximately linearly with the increase in fin height. On the other hand drain-induced barrier lowering (DIBL), subthreshold slope (S) and off-current IOFF are quite sensitive to the variations in fin width (at fixed fin height). We found that the lower Ldd and halo implant tilt angle (20–30°) are beneficial in reducing the SCEs and off-current. Finally, a comparison of the simulation results with electrical measurement data is presented, which shows fairly good agreement.

Improved simulation of VCSEL distributed Bragg reflectors

In this paper, the Floquet-Bloch theory (FBT) has been applied to the accurate simulation of distributed Bragg reflectors in vertical cavity surface emitting lasers (VCSELs). A number of comparisons with other methods largely used in commercial CAD tools is presented. Performance predictions for long-wavelength GaInAsP VCSELs are derived.

A 3-D hybrid Jiles-Atherton/Stoner-Wohlfarth magnetic hysteresis model for inductive sensors and actuators

The Jiles-Atherton (JA) theory of hysteresis is currently used in the majority of commercial CAD tools, mainly due to its implementation simplicity in fast and stable algorithms. The JA model provides precise results in the case of isotropic, polycrystalline, multidomain magnetic devices, where flux-reversal is governed by pinning mechanisms. Dynamic response of such devices, including Eddy-current loss and magnetic resonance, can also be accurately modeled. However, JA theory is not applied for three-dimensional (3-D) magnetization simulations and does not account for anisotropy that affects severely hysteresis curves of single-domain, thin-film devices, which are usually incorporated in miniature inductive sensors and actuators. In that case, the Stoner-Wohlfarth (SW) theory can be applied, which, however, does not account for dynamic response and incremental energy loss. In this work, we employ a virtual 3-D anisotropy-field vector calculated with SW theory that introduces magnetic feedback to the classical equation of Paramagnetism, in order to derive a proper 3-D "input" for the JA algorithm. This way, a hybrid 3-D JA/SW model is developed, which incorporates both models into one single formulation, capable of modeling simultaneously: 1) temperature effects, 2) pinning and Eddy-current loss, 3) magnetic resonance, and 4) uniaxial anisotropy, the orientation of which can be simulated to vary with time. The model that owns a solid physical basis has been implemented in a computation-efficient, stable algorithm capable of functioning with arbitrary excitation-field input. The algorithm has been successfully applied to model the behavior of a series of miniature Fluxgate magnetometers based on the Matteucci effect of thin glass-covered magnetic wires

CRYOGENIC HEMT NOISE MODELING BY ARTIFICIAL NEURAL NETWORKS

In this paper we report the development of an artificial neural network to extract a 17-element small-signal circuit model of high electron mobility transistors (HEMTs) and one associated noise temperature value. By this procedure, we are able to reproduce the small-signal and noise performance of several device types from only one measured scattering parameter set, one frequency point and one noise figure value. The employed noise figure is measured in input matched conditions (i.e. 50 Ω source impedance), namely F 50. The output noise temperature is associated to the drain-source resistance in the HEMT equivalent circuit according to the noise temperature model by Pospieszalski. The noise parameters of the device under test are then calculated by CAD simulation of the circuit and compared with measurement results. The trained network outputs were used by means of a commercial CAD tool, to simulate and fit measurements performed down to cryogenic temperatures with very good agreement. We observed that the difference that occurs between the expected value of the noise temperature and the average value calculated by the neural network leads to negligible variations in the behavior of the simulated noise parameters.

Analysis and design of band-pass frequency-selective surfaces using the FEM CAD tool

Three-dimensional (3D) full-wave analysis and design of bandpass frequency-selective surfaces (FSSs) is presented. By using the unique features of a unit cell and the periodic boundary conditions, infinite FSSs can be simulated. Wave propagation through FSSs, which is otherwise difficult to quantify, can be visualised by using a commercial CAD tool. The creation of the simulation model, interpretation and analysis of the outcome, and comparison with experimental results are presented for the square-slot and the square-loop-slot band-pass FSS. © 2004 Wiley Periodicals, Inc. Int J RF and Microwave CAE 14, 391–397, 2004.

A nonlinear dynamic S/H-ADC device model based on a modified Volterra series: Identification procedure and commercial cad tool implementation

A nonlinear, dynamic empirical model, based on a Volterra-like approach, was previously proposed by the authors for the time-oriented characterization of sample/hold (S/H) and analog-to-digital conversion (ADC) devices. In this paper, the experimental procedure for model parameter measurement is presented, as well as techniques devoted to the implementation of the model in the framework of the main commercial CAD tools for circuit analysis and design. Examples of simulations, performed both in the time and frequency domain on the model obtained for a commercial device, are proposed, which show the model's capability of pointing out the dynamic nonlinear effects in the S/H-ADC response.

ON GRAPH-BASED DESIGN OF FLOOR LAYOUTS

Knowledge-based tools assisting the designer in engineering represent further improvement of expert systems. The present paper shows how such software can be developed in the particular domain of floor layout design for buildings. The recently developed paradigm of hierarchical graphs is taken as the knowledge representation scheme. The user of the system is encouraged to undertake the search for rational solution at two levels. First, an analysis of functionality requirements for the designed object is performed. This results in a graph capturing main functions and relations between them. Further, this graph is mapped onto another graph depicting the floor layout in terms of areas and rooms. Both graphs produced by the user are checked against the constraints resulting from the requirements of the relevant code of practice. The final result is converted into the format accepted by a commercial CAD-tool in order to proceed with the detailed design.

ON GRAPH-BASED DESIGN OF FLOOR LAYOUTS

Knowledge-based tools assisting the designer in engineering represent further improvement of expert systems. The present paper shows how such software can be developed in the particular domain of floor layout design for buildings. The recently developed paradigm of hierarchical graphs is taken as the knowledge representation scheme. The user of the system is encouraged to undertake the search for rational solution at two levels. First, an analysis of functionality requirements for the designed object is performed. This results in a graph capturing main functions and relations between them. Further, this graph is mapped onto another graph depicting the floor layout in terms of areas and rooms. Both graphs produced by the user are checked against the constraints resulting from the requirements of the relevant code of practice. The final result is converted into the format accepted by a commercial CAD-tool in order to proceed with the detailed design. First Published Online: 26 Jul 2012

A finite-memory discrete-time convolution approach for the nonlinear dynamic modelling of S/H–ADC devices

A nonlinear dynamic “black box” model for sample-hold and analogue to digital conversion devices (S/H–ADCs) is proposed in this paper. It derives from the expansion of a Volterra-like series (previously introduced by authors for the general-purpose modelling of nonlinear dynamic systems) and it is based on a discrete convolution in the time domain, which describes the nonlinear dynamics of the system. The model carries out a functional description of the S/H–ADC nonlinear behaviour as the sum of two blocks which take separately into account the static and the purely dynamic contributions. Model characterization can be performed by means of a simple and reliable measurement procedure and the model analytical representation allows an easy implementation in the framework of commercial available CAD tools for circuit analysis and design. Preliminary experimental results, which validate the proposed approach, are presented in the paper together with some examples which show model capabilities in characterizing the device nonidealities under both DC and large-signal operating conditions.

Design of asynchronous circuits using synchronous CAD tools

Poor CAD support hinders wide acceptance of asynchronous methodologies, and asynchronous design tools are far behind synchronous commercial tools. A new design flow, NCL/spl I.bar/X, based entirely on commercial CAD tools, targets a subclass of asynchronous circuits called null convention logic. NCL/spl I.bar/X shows significant area improvement over other flows for this subclass.

A design environment for high-throughput low-power dedicated signal processing systems

A hierarchical automated design flow for low-energy direct-mapped signal processing integrated circuits is presented. A modular framework based on a combined dataflow graph and floorplan description drives automatic layout generation with commercial CAD tools. Automatic characterization of layout improves system-level estimates. Simplified physical design methodologies for low supply voltages are discussed. The flow is demonstrated on a 300-k transistor test-chip, a time-division multiple-access baseband receiver, and a soft-output Viterbi decoder. An example of architectural comparison of energy efficiency is presented.

A floating random-walk algorithm for extracting electrical capacitance

In 1991, we developed a floating random-walk algorithm to extract electrical capacitance in 2D structures. Since then, our work has evolved into a powerful commercial 3D CAD tool, QuickCap™, capable of finding capacitance in integrated circuits (ICs) represented by multi-gigabyte databases. The algorithm has proven to be exceptionally powerful and is now finding acceptance in an application area traditionally dominated by deterministic algorithms. We present the theory underlying the floating random-walk algorithm: a formulation of capacitance as an integral of infinite dimensionality evaluated by Monte Carlo integration. A single Monte Carlo sample of the integral corresponds to a floating random-walk. We also discuss performance characteristics of QuickCap and we summarize our contributions in other application areas.

Fault Modeling and Fault Simulation in Mixed Micro-Fluidic Microelectronic Systems

Developments in electronic/fluidic microsystems are progressing rapidly. The ultimate goal is to deliver products in the 10,000 fluidic reaction-wells range. Exciting applications include massive parallel DNA analysis and automatic drug synthesis. Until now, only functional testing has been used to “guarantee” the quality of micro-fluidic systems after manufacturing. In this paper, defect-oriented test approaches developed in analogue fault modeling and simulation have been used to predict for the first time the faulty behavior of micro-electronic fluidic microsystems. The modeling is targeted for use in complex electronic/fluidic microsystems employing commercial microsystem CAD tools. It enables a measure for the quality of these systems based on the performed (functional) tests and can be a guide for future test-stimuli generation and yield prediction.

High-Q and low-loss matching network elements for RF and microwave circuits

Experimental and theoretical results for microstrip line characteristics are included for several polyimide thicknesses and microstrip conductor widths. A closed-form expression for the equivalent dielectric constant of a multilayer dielectric structure is also derived to use with commercial CAD tools to design MMICs. Test data is also included for compact inductors processed using multilayer and multilevel plating on GaAs.

Dielectric connectors for multilayered RF integration

Using an array synthesis tool based on a modified differential evolution algorithm, it is shown that the position-phase synthesis exhibits improved pattern characteristics compared to both the phase only and position only synthesis of uniform amplitude antenna arrays. The design of an unequally spaced planar reflect-array and an active power combining reflect-array are presented. The unit cell of the active reflect-array consists of an amplifying active reflect-antenna designed using a novel dual polarized microstrip-T coupled patch antenna. Two modelling approaches are proposed for the active reflect-antenna and the modelling methods are compared with the experiments.A computationally efficient analysis of an H-slot in the ground plane of a microstripline is carried out using a transmission line model. To improve the accuracy in the resonant region of the H-slot and retaining the computational efficiency, an artificial neural network is combined with an efficient spectral domain method. An efficient analysis tool for a silicon micromachined H-slot coupled antenna is developed by combining the transmission line models of the H-slot and an aperture coupled antenna. The experimental results are compared with the theory showing good agreement.The analysis and design of a microwave amplifier based on non-resonant slot matching is carried out. It is seen that the designed slot matched amplifier has decreased layout size, improved gain and noise figure characteristics compared to a stub matched amplifier. An efficient method for the analysis of non-resonant slots is compared with other approaches showing good agreement. This points to the fact that non-resonant slot matched circuits can be designed with the same speed and efficiency as we design the traditional stub based matching circuits.To address the problem of bandwidth and performance of reflect-arrays we propose a dielectric resonator antenna with slotline stubs. As a preliminary step we design a dielectric resonator antenna with slotline feed and the experimental results are compared with those of a commercial CAD tool. Design and analysis of 3D interconnects based on non-radiative dielectric waveguides is carried out. At millimeterwave, these interconnects are useful for hybrid and multilayer integration techniques.

Concurrent checking for VLSI

This paper presents various concurrent checking techniques for VLSI, including self-checking circuits and concurent checking techniques for temporary faults based on time redundancy. It cautions that emerging technological constraints and application requirements will expend dramatically the use of these techniques. In particular, various industrial sectors (e.g. railway control, satellites, avionics, telecommunications, control of critical automotive functions, medical electronics, industrial control, etc), have increasing needs for concurrent checking features. Some of these applications concern mass production and should support the standardization of such techniques and the development of commercial CAD tools supporting them. Furthermore, drastic device shrinking and increasing operating speeds that accompany the technological evolution to deeper submicron, reduces significantly the noise margins and increases dramatically the impact of transient faults. In addition various spurious faults are becoming predominant and require very complex test conditions. Under such conditions, test pattern generation complexity and test length make impossible the detection of such faults. As a consequence, technological progress will be blocked quickly if no particular actions are undertaken to cope with increasingly high soft-error rates and undetected spurious faults resulting on timing errors. The paper will discuss these emerging requirements and problems and describe how concurrent checking can be used to cope with.

B-spline parametrization of finite element models for optimal design of electromagnetic devices

This paper presents B-spline parametrization method for the optimal shape design of electromagnetic devices. As an optimal design technique, the design sensitivity method based on the finite element method is used. Since the design variables of one-to-one correspondence with node points of finite element model can cause saw-tooth shape and serious accuracy problem, the design interface is parameterized into smooth curves using geometrical relation of design variables and node points of finite element model. B-spline technique used widely in computer graphics is capable of representing smooth curves and surfaces and can generate a wide variety of shapes. In addition, its geometry data can be easily connected to many commercial CAD tools. To show validity of the presented technique, we test two numerical examples: a magnet shape design problem for uniform magnetic field and a electrode shape design problem for uniform electric field.

An optimization procedure for MMIC large-signal amplifiers

An optimization procedure for GaAs integrated circuits to achieve both small-signal and large-signal performance is proposed. Besides the geometrical dimensions of the circuit passive elements, the process parameters are used as optimization variables to define two separate sets of optimization variables for small-signal and large-signal optimization. A large-signal MESFET model, based on simple expressions among circuit elements and process parameters, allows an effective implementation of the proposed optimization method in commercial CAD tools. © 1998 John Wiley & Sons, Inc. Microwave Opt Technol Lett 19: 386–388, 1998.