Concurrent checking for VLSI

Abstract

This paper presents various concurrent checking techniques for VLSI, including self-checking circuits and concurent checking techniques for temporary faults based on time redundancy. It cautions that emerging technological constraints and application requirements will expend dramatically the use of these techniques. In particular, various industrial sectors (e.g. railway control, satellites, avionics, telecommunications, control of critical automotive functions, medical electronics, industrial control, etc), have increasing needs for concurrent checking features. Some of these applications concern mass production and should support the standardization of such techniques and the development of commercial CAD tools supporting them. Furthermore, drastic device shrinking and increasing operating speeds that accompany the technological evolution to deeper submicron, reduces significantly the noise margins and increases dramatically the impact of transient faults. In addition various spurious faults are becoming predominant and require very complex test conditions. Under such conditions, test pattern generation complexity and test length make impossible the detection of such faults. As a consequence, technological progress will be blocked quickly if no particular actions are undertaken to cope with increasingly high soft-error rates and undetected spurious faults resulting on timing errors. The paper will discuss these emerging requirements and problems and describe how concurrent checking can be used to cope with.