Collector-emitter Offset Voltage Research Articles

Comparative investigation of InGaP/GaAs/GaAsBi and InGaP/GaAs heterojunction bipolar transistors

In this article the characteristics of In0.49Ga0.51P/GaAs/GaAs0.975Bi0.025 and In0.49Ga0.51P/GaAs heterojunction bipolar transistor (HBTs) are demonstrated and compared by two-dimensional simulated analysis. As compared to the traditional InGaP/GaAs HBT, the studied InGaP/GaAs/GaAsBi HBT exhibits a higher collector current, a lower base-emitter (B–E) turn-on voltage, and a relatively lower collector-emitter offset voltage of only 7 mV. Because the more electrons stored in the base is further increased in the InGaP/GaAs/GaAsBi HBT, it introduces the collector current to increase and the B–E turn-on voltage to decrease for low input power applications. However, the current gain is slightly smaller than the traditional InGaP/GaAs HBT attributed to the increase of base current for the minority carriers stored in the GaAsBi base.

High-performance AlGaInP tunneling heterostructure-emitter bipolar transistor

In this paper, a high-performance heterostructure-emitter bipolar transistor employing an AlGaInP quaternary compound tunneling layer is fabricated and demonstrated. In the studied device, a 50Å n-AlGaInP tunneling emitter layer together with a 200Å n-GaAs layer forms the heterostructure emitter to decrease the collector–emitter offset voltage. On the other hand, due to the relatively large valence band discontinuity (∼0.4eV) at AlGaInP/GaAs heterojunction and the small hole transmission coefficient across the AlGaInP tunneling layer, most of holes injecting from base to emitter will be blocked at AlGaInP/GaAs heterojunction and then high collector current and current gain are achieved. The experimental results exhibit a large collector current of 92mA, a large current gain of 446, and a relatively low offset voltage of only 45mV, respectively. Furthermore, a large current-gain cutoff frequency ft up to 63.7GHz is obtained for the device with a thin tunneling layer.

Comparative investigation of InP/InGaAs heterostructure-emitter tunneling and superlattice bipolar transistors

In this article, the characteristics of InP/InGaAs heterostructure-emitter bipolar transistors with 30 n-InP layer tunneling layers and a five-period InP/InGaAs superlattice are demonstrated and comparatively investigated by experimentally results and analysis. In the three devices, a 200 A n-In0.53Ga0.47As layer together with an n-InP tunneling emitter layer (or n-InP/n-InGaAs superlattice) forms heterostructure emitter to decrease collector-emitter offset voltage. The results exhibits that the largest collector current and current gain are obtained for the tunneling transistor with a 30 A n-InP tunneling emitter layer. On the other hand, some of holes injecting from base to emitter will be blocked at n-InP/n-InGaAs heterojunction due to the relatively small hole transmission coefficient in superlattice device, which will result in a considerable base recombination current in the n-InGaAs layer. Therefore, the collector current and current gain of the superlattice device are the smallest values among of the devices.

High-performance InP/InGaAs co-integrated metamorphic heterostructure bipolar and field-effect transistors with pseudomorphic base-emitter spacer and channel layers

In the InP/InGaAs metamorphic co-integrated heterostructure bipolar and field-effect transistors (BiFETs), the field-effect transistor (FET) with pseudomorphic channel layer was stacked on the top of the metamorphic heterostructure bipolar transistor (HBT) with pseudomorphic base–emitter spacer layers. In the FET, a relatively thin as well as heavily doped In0.65Ga0.35As pseudomorphic channel layer between two undoped InP layers was employed to enhance the gate forward operation voltage, drain current, and transconductance, simultaneously. On the other hand, after removing the top four layers of material structures, the studied HBT was fabricated on the metamorphic buffer layer. In the metamorphic HBT, the valence band discontinuity at InP/In0.65Ga0.35As heterojunction and emitter injection efficiency could be further extended than the conventional InP/In0.53Ga0.47As lattice-matched HBTs. Furthermore, the delta doping layer between two In0.65Ga0.35As spacer layers at emitter side could effectively eliminate the potential spike at base–emitter junction for reducing the collector–emitter offset voltage. Consequently, the co-integrated metamorphic devices show a good potential for mixed signal integrated circuits and systems applications.

Comparative investigation of InP/InGaAs abrupt, setback, and heterostructure-emitter heterojunction bipolar transistors

In this paper, the characteristics of InP/InGaAs abrupt, setback, and heterostructure-emitter heterojunction bipolar transistors (HBTs) are comparatively investigated by twodimensional simulation analysis. In the setback (heterostructure-emitter) HBT, a thin 50 A undoped In0.53Ga0.47As (n-In0.53Ga0.47As) layer is inserted between n-InP emitter and p+-InGaAs base layers to lower the energy band at emitter side for decreasing the collector-emitter offset voltage. The simulated results exhibits that the abrupt HBT has the largest current gain, the largest collector-emitter offset voltage, and the smallest unity gain cutoff frequency. While, the setback and heterostructure-emitter HBTs exhibit the smallest current gain and offcet voltage, respectively. Consequentially, the demonstration and comparison of the three-type HBTs provide a promise for design in circuit applications.

Study of Metamorphic Co-Integrated Heterostructure Bipolar and Field-Effect Transistors (BiFETs)

DC performance of InP/InGaAs co-integrated metamorphic semiconductor devices grown on GaAs substrate by combining heterostructure bipolar and field-effect transistors (BiFETs) is first demonstrated. In the metamorphic co-integrated BiFETs, the field-effect transistor is stacked on the top of the metamorphic heterostructure bipolar transistor (HBT). For the HBT, the potential spike at base-emitter junction is effectively eliminated for reducing the collector-emitter offset voltage by lowering the energy band at emitter side. A maximum current gain of 255 and a low offset voltage of 105 mV are obtained. Furthermore, with respect to the field-effect transistor, the thin InGaAs channel between two undoped InP layers is heavily doped and two-dimensional electron gas is formed in the channel. An extrinsic transconductance of 265 mS/mm and a saturation current density of 281 mA/mm are achieved.

A new InGaP/GaAs tunneling heterostructure-emitter bipolar transistor (T-HEBT)

Excellent characteristics of an InGaP/GaAs tunneling heterostructure-emitter bipolar transistor (T-HEBT) are first demonstrated. The insertion of a thin n-GaAs emitter layer between tynneling confinement and base layers effectivelty eliminates the potential spike at base-emitter junction and reduces the collector-emitter offset voltage, while the thin InGaP tunneling confinement layer is employed to reduce the transporting time across emitter region for electrons and maintain the good confinement effect for holes. Experimentally, the studied T-HEBN exhibits a maximum current gain of 285, a relatively low offset voltage of 40 mW, and a current-gain cutoff frequency of 26.4 GHz.

Comparative Studies on InGaP/GaAs Heterostructure-Emitter Bipolar Transistors with Tunneling- and Superlattice-Confinement Structures

This article first compares the difference of InGaP/GaAs heterostructure-emitter bipolar transistors (HEBTs) with tunneling- and superlattice-confinement structures at room temperature. In the two devices, the insertion of a thin n-GaAs layer at base-emitter junction helps to eliminate the potential spike and a relatively low collector-emitter offset voltage of about 40 mV is observed. The difference of tunneling mechanism will be investigated. Experimentally, a maximum current gain of 285 (176) and a current gain cutoff frequency of 26.4 (16.3) GHz are achieved for the tunneling (superlattice) device. As comparing the superlattice device, the tunneling device shows higher current gain at small B-E bias, while it has smaller current gain at large B-E bias.

Application of InGaAs/GaAs superlattice-base structure for InGaP/GaAs superlattice-emitter bipolar transistor

The performance of an InGaP/GaAs superlattice-emitter bipolar transistor with InGaAs/GaAs superlattice-base structure is demonstrated by experimental results. The injecting electrons from superlattice emitter are easy to transport into the superlattice-base region for promoting the collector current by tunneling behavior. Furthermore, the average energy gap of base regime is substantially reduced by the use of InGaAs/GaAs superlattice structure for the requirement of low turn-on voltage. Experimentally, the transistor exhibits a maximum common-emitter current gain of 295 and a relatively low collector-emitter offset voltage of only 16 mV. In particular, the ideality factor of collector current near to unity is obtained.

Comparison of heterostructure-emitter bipolar transistors (HEBTs) with InGaAs/GaAs superlattice and quantum-well base structures

The characteristics of InGaP/GaAs heterostructure-emitter bipolar transistors (HEBTs) including conventional GaAs bulk base, InGaAs/GaAs superlattice-base, and InGaAs quantum-well base structures are presented and compared by two-dimensional simulation analysis. Among of the devices, the superlattice-base device exhibits a highest collector current, a highest current gain and a lowest base–emitter turn-on voltage attributed to the increased charge storage of minority carriers in the InGaAs/GaAs superlattice-base region by tunneling behavior. The relatively low turn-on voltage can reduce the operating voltage and collector–emitter offset voltage for low power consumption in circuit applications. However, as to the quantum-well base device, the electrons injecting into the InGaAs well are blocked by the p+-GaAs bulk base and it causes a great quantity of electron storage within the small energy-gap n-type GaAs emitter layer, which significantly increases the base recombination current as well as degrades the collector current and current gain.

InGaP/GaAs heterojunction bipolar transistor grown on Si substrate with SiGe graded buffer layer

What is believed to be the first InGaP/GaAs heterojunction bipolar transistor grown on SiGe/Si substrate is reported. The collector-emitter offset voltage and the knee voltage of the device are ∼150 mV and <1 V, respectively. The maximum gain of the device is∼25 at collector current of∼100 mA. The collector and base ideality factor are ∼1.01 and ∼1.4, respectively. These results show the good potential for integrating the InGaP/GaAs heterojunction bipolar transistor on Si substrate using the compositionally graded SiGe buffer layer approach.

Simulated analysis for InGaP/GaAs heterostructure-emitter bipolar transistor with InGaAs/GaAs superlattice-base structure

A novel InGaP/GaAs heterostructure-emitter bipolar transistor (HEBT) with InGaAs/GaAs superlattice-base structure is proposed and demonstrated by two-dimensional analysis. As compared with the traditional HEBT, the studied superlattice-base device exhibits a higher collector current, a higher current gain of 246, and a lower base–emitter (B–E) turn-on voltage of 0.966 V at a current level of 1 μA, attributed to the increased charge storage of minority carriers in the InGaAs/GaAs superlattice-base region by tunneling behavior. The low turn-on voltage can reduce the operating voltage and collector–emitter offset voltage for low power consumption in circuit applications.

The Effect of Sulfur Treatment on the Temperature-Dependent Performance of InGaP/GaAs HBTs

Temperature-dependent dc characteristics and RF performances of InGaP/GaAs heterojunction bipolar transistors with sulfur treatment are systematically studied. The base-surface-recombination current, specific contact resistance, and sheet resistance of the studied devices can be effectively reduced by sulfur treatment. Practically, long-time sulfur treatment is not appropriate. In this paper, the studied device with the sulfur treatment for 12-15 min is a good choice. Experimentally, the collector-emitter offset voltage DeltaVCE and dc current gain with sulfur treatment can be substantially reduced and increased, respectively, over the 300-K-400-K temperature range. Moreover, as the temperature is increased, the device with sulfur treatment exhibits temperature-independent or thermally stable performances. The devices with sulfur treatment also exhibit improved RF characteristics

Improved dc and microwave performance of heterojunction bipolar transistors by full sulfur passivation

The temperature-dependent dc characteristics of InGaP∕GaAs heterojunction bipolar transistors with and without full sulfur passivation are systematically studied and demonstrated. The studied device with full sulfur passivation shows lower specific contact resistance ρC, lower sheet resistance Rsh, lower collector-emitter offset voltage ΔVCE, and higher dc gain βF than devices without sulfur passivation. The device with full sulfur passivation also exhibits better rf performance. In addition, the studied device with full sulfur treatment shows lower temperature variation coefficients of ρC,Rsh,ΔVCE, and βF. Thus, the device with sulfur treatment presents relatively temperature-independent characteristics that can extend the transistor action to higher temperature regimes.

Investigation of InP/InGaAs superlattice-emitter bipolar transistor with multiple negative-differential-resistance regions

The sequential tunneling behavior in InP/InGaAs superlattice-emitter bipolar transistors is demonstrated by theoretical analysis and experimental results. The tunneling mechanism in the InP/InGaAs superlattice structures is analyzed by theoretical calculation. Due to the weak coupled tunneling mechanism, the interesting multiple negative-differential-resistances (NDRs) resulting from the creation and extension of high-field domain in the superlattice are observed at room temperature. Experimentally, the transistor performances, including a high current gain of 454, a low collector–emitter offset voltage of 80 mV, and a pronounced multiple NDRs, are achieved. The proposed structures may provide good potential for signal amplifiers and multiple-valued logic circuit applications.

Characteristics of InGaP/GaAs heterojunction bipolar transistors (HBTs) with sulfur treatments

The characteristics of the InGaP/GaAs heterojunction bipolar transistors (HBTs) with sulfur treatment are studied and demonstrated. Based on the use of sulfur passivation, the series resistance of a base–emitter B–E junction can be effectively reduced and the series resistance dominant regimes (decrease of current gain) are presented at a higher collector current regime. The device with sulfur treatment can be operated under extremely low collector current ( I C ≅ 1 0 − 11 A ) region, which offers the promise for low-power electronics applications. It is known that, from experimental results, the too long time for sulfur treatment is not necessary. Furthermore, the studied devices with sulfur treatment can remarkably reduce the collector–emitter offset voltage Δ V CE and emitter size effect, and improve the high-frequency performance.

DC Characterization of InP/InGaAs Tunneling Emitter Bipolar Transistor

An InP/InGaAs tunneling emitter bipolar transistor (TEBT) is studied and demonstrated. From the simulation results, the band diagram, tunneling transmission, and carrier distribution of the device are analyzed as functions of barrier thickness. The higher the emitter injection efficiency, the higher the current gain and the larger the current drivability for the device studied by employing a tunneling barrier layer of suitable thickness. In addition, experimentally, InP/InGaAs TEBT has been fabricated successfully. Due to its excellent tunneling barrier structure, the studied device can be operated under an extremely wide collector current range. The operation range is larger than 11 decades of collector current (10-12 to 10-1 A). Moreover, the studied device exhibits a very small collector-emitter offset voltage (ΔVCE) of 40 mV and an extremely wide operation range of output current. Thus, the studied device is suitable for low-voltage and low-power circuit applications.

The influence of a [formula omitted]-doped sheet on DC performances of InP/InGaAs heterojunction bipolar transistors

In this paper, we report the influence of a δ -doped sheet on the DC characteristics of InP/InGaAs δ -doped heterojunction bipolar transistors. The employment of a δ -doped sheet at the base–emitter (B–E) junction efficiently eliminates the potential spike at the B–E junction, lowers the collector–emitter offset voltage, and increases the confinement effect for holes, simultaneously. An analytical model related to the elimination of the potential spike and the components of base recombination currents is developed to investigate the transistor performances. Experimentally, for the studied device with a δ -doping density of 2×10 12 cm −2, a maximum current gain of 455 and a low offset voltage of 55 mV are achieved. The experimental results are consistent with the theoretical analysis.

Influence of spacer layer on InP/InGaAs δ-doped heterojunction bipolar transistors

In this paper, the influence of spacer layers on DC performance of InP/InGaAs δ-doped heterojunction bipolar transistors (HBT's) is investigated by theoretical analysis and experimental results. As compared to previous δ-doped HBT's, the studied device has another left-side InGaAs spacer added between δ-doped sheet and InP emitter layers at base–emitter (B–E) junction. The left-side spacer more effectively helps to maintain the integrity of uniform-doped InP emitter and the quality of interface; reduce the emitter barrier for electrons, decrease the collector–emitter offset voltage, and increases the confinement effect for holes. An analytical model related to the potential spike at B–E junction and base recombination current is developed to demonstrate the transistor performances. Experimentally, transistor performances with a maximum current gain of 455 and a low offset voltage of 55 mV are achieved.

Application of InGaP/GaAs/InGaAs step-compositional-emitter structures for multiple-route switch

In this paper, a functional InGaP/GaAs/InGaAs step-compositional-emitter heterojunction bipolar transistor (SCEBT) is demonstrated. The excellent transistor performance, including a high current gain and a low collector–emitter offset voltage, is achieved under normal operation mode. In particular, an interesting three-state S-shaped negative-differential-resistance (NDR) switch is observed under inverted operation mode at room temperature because of the reduction of base barrier height and discontinuous confinement effects for electrons in a InGaP/GaAs heterojunction and InGaAs quantum well, respectively. The three-terminal base-controlled NDR characteristics and multiple-valued logic applications are also investigated. Consequently, the transistor action and switching characteristics of the studied SCEBT are promising for signal amplifier and logic circuit applications.