Coaxial Through Silicon Via Research Articles

Design of Silicon Core Coaxial TSVs to Reduce Crosstalk Effects for 3D IC Applications

This paper presents the effectiveness of the copper (Cu)-based coaxial through silicon vias (CTSVs) to reduce crosstalk noise and propagation delay. In the proposed CTSVs, the polymer liners are used as insulating material which cancels the crosstalk functional failures. The impacts of the proposed CTSVs on the electrical performance are noticed for different parameters and properties of the material. Simulations of the proposed CTSVs are executed using the standard HSPICE and SYMICAD tools. The results indicated that the effects of crosstalk are reduced using the polymer liners instead of silicon dioxide (SiO2) liners in the proposed CTSVs. The electrical performances of the proposed CTSVs are investigated for various thicknesses of Cu and BCB. Furthermore, a comparative study has been carried out for the SiO2 and benzocyclobutene (BCB) liners. It is observed that BCB liner-based CTSVs crosstalk noise and delay values are reduced by up to 25.06% and 27.8% compared to the SiO2 liner-based TSVs.

Interface Reliability Modeling of Coaxial Through Silicon Via Based on WOA-BP Neural Network

Abstract Due to the complex structure and thermal mismatch of coaxial through silicon via (TSV), cracks easily occur under thermal load, leading to interface delamination or spalling failure. The reliability issue of coaxial TSV is important for its application in three-dimensional packaging, so it is of great significance to predict the crack trend and evaluate the reliability of coaxial TSV. In this paper, an algorithm model with the combination of whale optimization algorithm (WOA) and back propagation (BP) neural network for the reliability prediction of coaxial TSV is proposed. Based on finite element method (FEM), the training and validation datasets of the energy release rates (ERR) of the crack at the critical interface are calculated to construct the deep learning neural network. Six key structure parameters affecting the reliability of coaxial TSV are selected as the input values of the BP neural network. The maximum relative error of whale optimization algorithm optimized back propagation (WOA-BP) neural network model is 0.88%, which is better than the prediction results of the traditional BP and genetic algorithm (GA) optimized BP models. The WOA-BP neural network model was also compared with BP and GA-BP neural network models with four error metric models. It is verified that WOA-BP neural network model has the best prediction performance. The proposed model can be used to achieve improved prediction accuracy for the interface reliability of coaxial TSV under complex structural conditions since it has higher accuracy and stronger robustness.

Efficient Thermal-Stress Coupling Design of Chiplet-Based System with Coaxial TSV Array.

In this research, an efficient thermal-stress coupling design method for a Chiplet-based system with a coaxial through silicon via (CTSV) array is developed by combining the support vector machine (SVM) model and particle swarm optimization algorithm with linear decreasing inertia weight (PSO-LDIW). The complex and irregular relationship between the structural parameters and critical indexes is analyzed by finite element simulation. According to the simulation data, the SVM model is adopted to characterize the relationship between structural parameters and critical indexes of the CTSV array. Based on the desired critical indexes of the CTSV array, the multi-objective evaluation function is established. Afterwards, the structural parameters of the CTSV array are optimized through the PSO-LDIW algorithm. Finally, the effectiveness of the developed method is verified by the finite element simulation. The simulated peak temperature, peak stress of the Chiplet-based system, and peak stress of the copper column (306.16 K, 28.48 MPa, and 25.76 MPa) well agree with the desired targets (310 K, 30 MPa, and 25 MPa). Therefore, the developed thermal-stress coupling design method can effectively design CTSV arrays for manufacturing high-performance interconnect structures applied in Chiplet-based systems.

Thermal-Stress Coupling Optimization for Coaxial through Silicon Via

In this paper, a thermal-stress coupling optimization strategy for coaxial through silicon via (TSV) is developed based on the finite element method (FEM), artificial neural network (ANN) model and particle swarm optimization (PSO) algorithm. In order to analyze the effect of design parameters on the thermal-stress distribution of coaxial TSV, the FEM simulations of coaxial TSV are conducted by COMSOL Multiphysics. The structure of coaxial TSV is symmetric. The mapping relationships between the design parameters and performance indexes are described by ANN models based on the simulation data of FEM. In addition, the multi-objective optimization function is formulated based on the desired performance indexes, and then the design parameters are optimized by the modified PSO algorithm. Based on the optimized design parameters, the effectiveness of the developed method is validated by FEM simulations. The simulated performance indexes agree well with the desired ones, which implies that the design parameters of coaxial TSV can be optimized to control the thermal-stress distribution. Therefore, the thermal-stress coupling optimization of coaxial TSV can achieve thermal-stress management to improve its reliability.

Electrical Characterization of Through-Silicon-via-Based Coaxial Line for High-Frequency 3D Integration (Invited Paper)

Through-silicon-via (TSV)-based coaxial line techniques can reduce the high-frequency loss due to the low resistivity in the silicon substrate and thus can improve the efficiency of vertical signal transmission. Moreover, a TSV-based coaxial structure allows easily realizing the impedance matching in RF/microwave systems for excellent electrical performance. However, due to the limitations of existing available dielectric materials and the difficulties and challenges in the manufacturing process, ideal coaxial TSVs are not easy to obtain, and thus, the achieved electrical performance might be unexpected. In order to increase the flexibility of designing and manufacturing TSV-based coaxial structures and to better evaluate the fabricated devices, modeling and analysis theories of the corresponding high-frequency electrical performance are proposed in the paper. The theories are finally well validated using the finite-element simulation results, hereby providing guiding rules for selecting materials and improving manufacturing techniques in the practical process, so as to optimize the high-frequency performance of the TSV structures.

Impact of Polymer Liners on Crosstalk Induced Delay of Different TSV Shapes

The performance of a through silicon via (TSV) based 3D integrated circuit technology is primarily dependent on the choice of an appropriate liner material. The most commonly used liner material, SiO2, is undergoing considerable reliability challenges such as coefficient of thermal expansion (CTE) mismatch, scallop formation, and interfacial delamination related problems. Therefore, TSVs employed with a polymer liner have achieved significant attention in recent years due to their low dielectric constant and excellent step coverage along the via surface that can effectively reduce thermal stress and crosstalk induced delay. This paper presents a comprehensive and accurate RLGC model for different via shapes, considering the impact of various liner materials on the crosstalk induced delay. Considering an accurate via geometry and material properties at 32 and 45 nm technology, the proposed equivalent RLGC parameters include the cumulative effects of TSV metal, liner, bump, and the silicon substrate. The aforementioned parameters are used to model a novel T-type equivalent electrical network of cylindrical, tapered, and coaxial TSVs considering a coupled driver-via-load (DVL) setup. The proposed equivalent models of different via shapes are used to demonstrate the worst-case crosstalk induced delay in TSVs under the influence of various liner materials. Considering a tapered TSV, a significant improvement in crosstalk induced delay at 32 nm w.r.t. 45 nm technology is observed as 53.5%, 33.76%, and 19.12% at aspect ratios of 2.4, 3, and 4, respectively for the BCB liner.

Symmetrical Multilayer Dielectric Model of Thermal Stress and Strain of Silicon-Core Coaxial Through-Silicon Vias in 3-D Integrated Circuit

In this work, an analytical model of strain and stress of symmetrical multilayer medium is proposed to solve the thermal problem that occurs in silicon-core coaxial through-silicon vias (S-CTSV). Based on the 3-D Kane–Mindlin theory, the proposed analytical model of strain considers both elastic strain and thermal strain. In addition, the stress is discussed in segments using planar stress and Hooke’s law in the model of S-CTSVs to improve the accuracy. The results indicate that the average relative errors in terms of strain and stress between the results of the proposed analytical model and the finite-element method (FEM) were 4.06% and 0.17%, respectively. Compared with the back propagation (BP) neural network-based prediction algorithm, the average relative errors in strain and stress between the proposed model and the FEM were decreased by 3.97% and 3.23%, respectively. Moreover, the stress of three different CTSVs was also compared. The stress of the proposed S-CTSVs model was lower than those of the two traditional CTSVs, which ensure higher reliability. The results in this article would provide some design guides for S-CTSVs in 3-D integration.

Modeling of the RF Coaxial TSV Configuration Inside the Silicon Interposer With Embedded Cooling Cavity

In this article, a low-loss RF coaxial through-silicon vias (TSVs) (C-TSVs) configuration in the silicon interposer with the embedded cooling cavity is proposed. For the single C-TSV array passing through the embedded cooling cavity, the transmission losses with different coolants were compared. The insertion loss immersed in FC770 is 0.14 dB at 40 GHz, which is closed to the typical C-TSV interposer (0.2 dB). It is much smaller than the deionized water (6.49 dB) one. The optimal spacing of multiple C-TSV arrays filled with FC770 coolant is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$600~\mu \text{m}$ </tex-math></inline-formula> (vertical transmission of 0.16 dB at 40 GHz). When the cooling cavity is embedded in the interposer with FC770 coolant, the maximum surface temperature of the power devices can be less than 56.8 °C at 250 W/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> heat flux. Compared with the solid silicon interposer, the maximum von Mises thermal stress of the C-TSV interposer with the embedded cooling cavity can be reduced by 44.8%.

A Miniatured Passive Low-Pass Filter With Ultrawide Stopband Based on 3-D Integration Technology

By using integrated lumped elements based on through-silicon via (TSV) technology, a 3-D low-pass filter (LPF) with ultracompact size and ultrawide stopband is proposed. The 3-D magnetic coupling is enhanced between microsize spiral inductors to increase the mutual inductance and improve the high-frequency performance. A coaxial TSV with enhanced capacitance in high resistivity silicon (HRS) is utilized both as capacitor and as a vertical interconnection without any overhead in area and routing. The 3-D nature of the proposed filter yields a miniaturized size of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.2\times0.10$ </tex-math></inline-formula> mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The LPF is analyzed with equivalent circuit model and validated with the well-matched <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$S$ </tex-math></inline-formula> -parameters obtained by finite element method simulation and measurement. With −3-dB cutoff frequency at 2.6 GHz, the LPF exhibits an insertion loss below 1 dB, a reflection loss over 17 dB in the passband, and a suppression level over 20 dB from 5.28 up to 40 GHz in the stopband.

Design of compact LC lowpass filters based on coaxial through-silicon vias array

By utilizing coaxial through-silicon via (TSV) technology, compact LC low-pass filters (LPFs) are proposed. Firstly, several capacitors based on coaxial TSV are investigated, in detail, by means of analytic calculation, finite element method (FEM) simulation, and measurement. Secondly, a formula for the inductance of coaxial TSV-based spiral inductors is proposed and verified by FEM simulations and measurements. Finally, based on the investigation of TSV-based capacitors and inductors, an analytical model of the proposed LC LPFs based on 2 ×4,2×5,2× 6, and 2 × 7 coaxial TSV arrays is proposed, and the equivalent circuit model and the finite element method (FEM) model are established in ADS and HFSS, respectively. The LPFs are fabricated and verified through measurements. In the proposed LPFs, coaxial TSVs are used as capacitors and inductors simultaneously, which leads to a more compact size. The parasitic capacitance of the inductors can, helpfully, induce a notch point for the proposed LPFs in stopband and improve the roll-off rate.

Electrical modeling of carbon nanotube‐based shielded through‐silicon vias for three‐dimensional integrated circuits

AbstractIn this article, two kinds of shielded carbon nanotube (CNT) through‐silicon vias (TSV) are proposed and investigated for high‐density three‐dimensional integrated circuits (3‐D ICs). First, vertical aligned CNT array is inserted into a single hole, and two isolated metal pads, that is, the central circular and outer annular pads, are deposited onto the surface to make distinct conduction paths. The shielded CNT TSV, which can also be named as coaxial TSV, is formed, with the semiconducting CNTs utilized to suppress lateral conductance. Based on a similar concept, the shielded differential CNT TSV is developed. By virtue of the proposed shielded CNT TSVs, the chip area can be saved significantly. The equivalent circuit models are established for the proposed shielded CNT TSVs. A passive equalizer is designed to improve the signal quality for shielded differential CNT TSV. Finally, the potential applications of the proposed TSVs in 3‐D IC power distribution network design are investigated.

Electrical–Thermal Cosimulation of Coaxial TSVs With Temperature-Dependent MOS Effect Using Equivalent Circuit Models

A coupled electrical–thermal cosimulation with consideration of the temperature dependence of the metal-oxide-semiconductor (MOS) effect is performed for coaxial through silicon vias (C-TSVs) by using equivalent electrical and thermal circuit models. In the equivalent electrical circuit (EEC) model, the dependence of the MOS capacitance on bias voltage, operation frequency, oxide charge density, and temperature is studied, and further verified by measurement results from a previous publication. A 3-D equivalent thermal circuit (ETC) model with lump components, including thermal resistance and thermal capacitance analytically calculated from the geometry and material parameters of C-TSVs, is proposed for transient thermal simulation. The accuracy of the EEC and ETC models is verified by comparisons with full-wave simulations. Transient electrical–thermal co-simulation is performed for the C-TSVs with the EEC and ETC models. Results reveal that the temperature dependence of depletion width and corresponding MOS capacitance leads to considerable variations in the S-parameters of C-TSVs.

Crack-Free Fabrication and Electrical Characterization of Coaxial Ultra-Low-Resistivity-Silicon Through-Silicon-Vias

Ultra-low-resistivity-silicon (ULRS) coaxial through-silicon-vias (TSVs) employ silicon pillar as the central conductor, which simplifies the fabrication process and exhibits good electrical characteristics. However, microcracks that may appear on silicon pillars degrade the reliability and electrical properties. In this work, the main cause of microcracks is investigated experimentally and an optimized fabrication process is proposed to avoid microcracks, which includes a two-step chemical mechanical polishing for frontside Benzocyclobutene overburden layer removal and a two-step backside TSVs reveal process featuring mechanical grinding with a safety margin followed by chemical mechanical polishing. Utilizing the proposed method, crack-free ULRS coaxial TSVs were successfully fabricated. In addition, the electrical properties of TSVs including ${I}$ - ${V}$ curves and ${S}$ -parameters were characterized under various temperatures, and the results demonstrates that the coaxial TSVs exhibit good impedance matching and low insertion loss up to 50 GHz even under 125°C.

Through-Silicon Via-Based Capacitor and Its Application in LDO Regulator Design

Using coaxial through-silicon technologies, a new 3-D capacitor integrated on a silicon interposer is proposed. The capacitance of coaxial through silicon via (CTSV) capacitors is extracted, analyzed, and compared. The results obtained from the analytical model and the finite-element method exhibit good agreement with various design parameters, and the error between the proposed model and measurement remains less than 7.41%. Due to high capacitance density up to 22.4 nF/mm2, the 3-D capacitor is adopted as a decoupling capacitor for the on-chip low-dropout (LDO) regulator design. The proposed LDO is developed in a 180-nm CMOS technology and shows unique advantages regarding the power supply rejection (PSR) performance, quiescent current, and area compared with that of the conventional LDOs with off-chip capacitors and capacitor-less (CL) LDOs.

Fabrication and measurement of 3D LPF based on coaxial TSV

The implementation of mainstream passive low-pass filters (LPFs) remains a challenge to satisfy the requirements of small size and compatibility with standard CMOS process. Fortunately, the emerging technology of through-silicon via (TSV) offers a possible solution to this issue by developing 3D LPF architecture. A 3D LPF based on coaxial TSV is exploited by fabrication and measurement. The measurement result shows good agreement with that obtained by finite element method.

Partial Coaxial Through-Silicon via for Suppressing the Substrate Noise in 3-Dimensional Integrated Circuit

In this paper, a novel through-silicon via (TSV) structure, named partial coaxial TSV (PC-TSV), is proposed to suppress TSV-induced substrate noise. In this structure, the via is surrounded by a benzocyclobutene (BCB) layer, and a grounded metal ring placed at one end. The BCB layer can effectively reduce the leakage of the signal to the substrate, and the metal ring provides a low impedance path for the substrate noise. An equivalent RLGC model of this structure is also established, and it is verified by simulated result from CST. Then, the performance of PC-TSV is compared with that of the traditional TSV, TSV with p+ layer, and TSV with p+ guard ring. Analysis results in frequency domain indicate PC-TSV has a larger $\vert \text{S}_{21}\vert $ and less near-end crosstalk than other three structures. Additionally, analysis results in time domain show that the substrate voltage noise of this structure is obviously reduced compared with the TSV with p+ layer and TSV with p+ guard ring. Also, a feasible process flow for this structure is given and it is simpler than that for traditional coaxial TSV.

Fabrication and RF Property Evaluation of High-Resistivity Si Interposer for 2.5-D/3-D Heterogeneous Integration of RF Devices

In this paper, a high-resistivity silicon (HR-Si) interposer integrated with through-silicon via (TSV) electrically grounded coplanar waveguide (CPW) line is presented for 2.5-D/3-D heterogeneous integration of radio frequency (RF) microelectronics devices. In addition, design of TSV interconnection composed of two coaxial ladder-hollow-annular Cu (copper) TSVs of different diameters is utilized to maintain a sufficient freedom for strict standard cleaning to avoid Si resistivity degradation. The formation of the coaxial ladder TSV structure is more beneficial to the subsequent plating process because it reduces the aspect ratio of TSV vias. Hollow-annular Cu TSV is manufactured in order to reduce the problem of mismatch in coefficient of thermal expansion among TSV’s constituent materials. A layer of Au (aurum) film is utilized to passivate the exposed Cu surface of Si interposer. Au is widely used in III–V groups’ devices because of the good compatibility with photonic integrated circuits, conductivity, and corrosion resistance. HR-Si interposer with TSV grounded CPW line and test structure is fabricated and characterized. With the monitoring test results, it can be found that it changes little in the resistivity of Si substrate, though the whole process, which is a basic requirement for RF performance. RF property test results show that the insertion loss is about −0.20 dB/mm at 10 GHz for the presented TSV grounded CPW line and −0.02 dB per TSV. These test results are better than the traditional design. To verify its applicability to 2.5-D/3-D heterogeneous integration, RF microelectronics die is assembled on TSV interposer and tested, and the test results prove that it works properly.

Electrical Modeling and Characterization of Silicon-Core Coaxial Through-Silicon Vias in 3-D Integration

Based on the extracted resistance, inductance, capacitance, and conductance parameters, this paper introduces the distributed transmission line model of silicon-core coaxial through-silicon vias (CTSVs), in which the vertical interconnect is made of a Cu-coated silicon pole. The proposed model is validated against a commercial electromagnetic simulation tool, showing it is highly accurate up to 100 GHz. Using the proposed model, the impact of various material properties and physical parameters on the electrical performance of the silicon-core CTSVs is investigated. It is observed that the thickness of the plated Cu and isolation dielectric are two important parameters that determine the electrical performance of silicon-core CTSVs. Performance comparison shows that the proposed silicon-core CTSVs provide a comparable performance to standard Cu-based CTSVs and better performance to the conventional signal-ground TSV pairs. The results in this paper would provide some design guides for silicon-core CTSVs in 3-D integration.

Electrical Modeling and Analysis of Cu-CNT Heterogeneous Coaxial Through-Silicon Vias

An equivalent-circuit model of Cu-carbon nanotube heterogeneous coaxial through-silicon vias (HCTSVs) in 3-D integrated circuits (3-D ICs) is proposed in this paper. Based on the complex effective conductivity method, the resistances and inductances of Cu-single walled carbon nanotube (SWCNT) HCTSVs and Cu-multi walled carbon nanotube (MWCNT) HCTSVs are compared with that of Cu coaxial through-silicon vias (CTSVs). Furthermore, using the proposed model, the magnitudes of their insertion losses are compared. It is shown that the transmission performance of Cu-SWCNT HCTSVs with higher metallic fraction and Cu-MWCNT HCTSVs is better than that of Cu CTSVs, and the improvement of Cu-MWCNT HCTSVs is more obvious at high frequencies. Finally, the transmission characteristics of Cu-MWCNT HCTSVs are analyzed deeply to provide helpful design guidelines for them in future high-speed 3-D ICs.

Modeling and Characterization of Coaxial Through-Silicon Via With Electrically Floating Inner Silicon

In this paper, coaxial through-silicon via (C-TSV) is modeled and studied with the consideration of electrically floating inner silicon substrate. Nonlinear capacitances of the central via and the outer shielding shell are accurately captured by solving cylindrical Poisson equation. By employing symbolically defined device block, the nonlinear capacitances of the C-TSV with electrically floating inner silicon are combined into the equivalent circuit model, and their impacts on the electrical characteristics are examined.