Abstract

Using coaxial through-silicon technologies, a new 3-D capacitor integrated on a silicon interposer is proposed. The capacitance of coaxial through silicon via (CTSV) capacitors is extracted, analyzed, and compared. The results obtained from the analytical model and the finite-element method exhibit good agreement with various design parameters, and the error between the proposed model and measurement remains less than 7.41%. Due to high capacitance density up to 22.4 nF/mm2, the 3-D capacitor is adopted as a decoupling capacitor for the on-chip low-dropout (LDO) regulator design. The proposed LDO is developed in a 180-nm CMOS technology and shows unique advantages regarding the power supply rejection (PSR) performance, quiescent current, and area compared with that of the conventional LDOs with off-chip capacitors and capacitor-less (CL) LDOs.

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.