CMOS Technology Research Articles

Analysis and Design of an Active Rectifier for Wireless Power Transfer in 90 nm CMOS Technology

In this paper, an analysis and design of a new active rectifier used for wireless power transfer applications using 90 nm CMOS technology are presented. The proposed architecture of the active rectifier has mainly been chosen to improve the VCE and the PCE and also to eliminate the need for large on-chip capacitors. The proposed circuits eliminate the drop needed for conduction by replacing diode-connected nMOS devices with others controlled by an active circuit. The new architecture of the active rectifier has been designed, simulated, and laid out by Cadence Virtuoso using TSMC 90nm technology. The input range is 0–5 V, and the output voltage is 2.14 V, with the VCE and the PCE values of 82.9% and 86.2%, respectively. The layout utilizes a compact space of 0.0597 mm2 within the TSMC CMOS 90 nm technology.

A Novel DTSCR Structure with High Holding Voltage and Enhanced Current Discharge Capability for 28 nm CMOS Technology ESD Protection.

To cope with the much narrower ESD design window in 28 nm CMOS technology, a novel diode-triggered silicon-controlled rectifier with an extra discharge path (EDP-DTSCR) for ESD protection is proposed in this paper. Compared with the traditional DTSCR, the proposed DTSCR has an enhanced current discharge capability that is achieved by creating a slave SCR path in parallel with the master SCR path. Moreover, the improved triggering and holding characteristic can be obtained by the proposed EDP-DTSCR. By sharing the anode emitter junction, a slave SCR path is constructed that is symmetrical to the position of the master SCR path to add an additional ESD discharge path to the EDP-DTSCR. In this way, the current discharge capability of the entire device is obviously improved. The TCAD simulation result shows that the proposed device has a remarkably lower on-resistance compared with the traditional DTSCR and the DTSCR with p-type guard ring (PGR-DTSCR). In addition, it is structurally optimized to further increase the holding voltage and reduce the trigger voltage to improve the anti-latching capability of the device, which is more conducive to the ESD protection window application of 28 nm CMOS technology.

Low Noise Operational Amplifier using Current Driving Bulk by CMOS Technology

A reverse substrate bias operational amplifier using existing driver technology has been designed and implemented using 0.25μm CMOS process to achieve high noise performance. Op amps are efficient and versatile devices. Its applications include signal conditioning, custom conversion, analog equipment, competitive simulation, and various electronic industries meeting custom design requirements. As the trend of low voltage devices continues, designing high-performance analog circuits becomes increasingly difficult. The main module of analog circuits is the work amplifier. In large electronic devices, there is a trade-off between speed, power, and gain, among other drawbacks. Additionally, in order to reduce costs and integrate analog and digital circuits on a single die, analog designers must face the challenges of using the CMOS process. Design and implementation are done in 0.25μm technology using TSMC libraries and with the help of Tanner tools.

New, Fast, High-Performance Level Shifter for Buck DC-DC Converter in 180nm CMOS Technology

To reduce power dissipation, the dual supply voltage approach is required for analog circuits in the on-chip integrated circuits. In this paper, a novel circuit of the level shifter for Buck DC-DC Converter using cross-coupled configuration is presented. The proposed work of this paper uses this level shifter to converter voltage of 1.8V to 5V at 180 nm CMOS Technology in Cadence Virtuoso Tool. The propagation delay, energy/transition, and static power were 182.42pS, 0.01 fJ/Transition, and 6 fW, respectively. The final design area is only 60.142 μm2.

On-Chip Tunable Active Inductor Circuit for Radio Frequency Ics

The work presents a design of a gyrator-based on-chip tunable active inductor (AI) which can become an integral part of high-frequency integrated circuits. The proposed AI uses the Floating gate technology-based PMOS (FGPMOS) simulation model, where the on-chip, non-volatile programming ability of FGPMOS is used as a tunable active feedback resistor. The circuit specifications are first derived for the application at 800MHz to 2GHz. The design is simulated at 350nm CMOS technology and shows a temperature sensitivity of 0.13mV/oC as well as a noise sensitivity of about 10.97nV/Hz. The precise programming range of inductance value from 3nH to 9nH can be achieved. The circuit has a power dissipation of 5.02mV and a moderately high-quality factor of about 120. The layout of the proposed circuit has been designed on Cadence Virtuoso and fabricated at ON-Semiconductor, C5 CMOS process foundry of MOSIS fabrication service, USA. The complete design has a chip area of 18x30µm2. The fabricated results illustrate the on-chip tuning ability of the proposed AI from 3nH to 7nH with the help of externally applied Tunnelling and Injection voltages, respectively. The proposed design also simulates a tunable bandpass filter and a tunable Low Noise Amplifier.

Lossless Grounded Capacitance Multiplier Based On Two CFOAs

A new lossless grounded capacitance multiplier (GCM) based on two current-feedback operational amplifiers (CFOAs) is proposed. The proposed circuit is built with a least number of passive elements. The capacitor is selected as grounded in the proposed circuit, while one resistor is grounded and the other is floating. The proposed GCM has low power consumption and a very large multiplying factor. The passive element matching conditions are not necessary for the designed GCM. The SPICE program is used for the simulations, and all the simulations are performed with 0.18µm CMOS technology parameters. The simulation results verify the ideal results from 10Hz to 15MHz. Further, the designed GCM is tested in the application circuit, which is a second-order passive filter. The experiments of the desgined GCM are achieved by using AD844s instead of CFOAs.

Logical Resolving-Based Methodology for Efficient Reliability Analysis.

With the CMOS technology downscaling to the deep nanoscale, the aging effects of devices degrade circuit performance and even lead to functional failure. The stress analysis is critical to evaluate the influence of aging effects on digital circuits. Some related analytical work has recently focused on reliability-aware circuit analysis. Nevertheless, the aging dependence among different devices is not considered, which will induce errors of degradation evaluation in the digital circuit. In order to improve the accuracy of reliability-aware static timing analysis, an improved analytical method is proposed by employing logical resolving. Experimental results show that the proposed method has a better evaluation accuracy of aging path delay than traditional strategies. For aging timing evaluation on aging paths, excessive pessimism can be reduced by employing the proposed method. And, a 378× speedup is achieved while having a 0.56% relative error compared with precise SPICE simulation. Moreover, the circuit performance sacrifice of an aging-aware synthesis flow with the proposed method can be decreased. Due to the high efficiency and high accuracy, the proposed method can meet the speed demands of large-scale digital circuit reliability analysis while achieving transistor simulation accuracy.

Design of XOR-NMOS switch based kickback noise reduction technique for dynamic comparators

We have integrated dynamic comparators to meet the rigorous demands for ultra-low power and miniaturized ADC converters, which are essential for optimizing power efficiency, speed, and overall performance within ADC circuits. These comparators scrutinize input signal voltages against predefined reference values, with traditional dynamic comparators offering distinct advantages such as minimal power consumption, elevated input impedance, and robust noise tolerance. However, their susceptibility to kickback noise is a significant drawback, substantially hindering operational efficiency. Our innovative solution focuses on noise reduction, strategically deploying sampling switches and XOR gates between the regenerative nodes and comparator inputs to create an effective noise isolation barrier. Validation through exhaustive simulations using Mentor Graphics software within the framework of state-of-the-art 45 nm CMOS technology showcases the effectiveness of our approach. Scientifically, our work holds profound significance. Addressing the pervasive issue of kickback noise in dynamic comparators has the potential to reshape the ADC technology landscape. This advancement promises to significantly enhance the performance of existing systems, paving the way for more efficient and compact ADC converters. Our research contributes to various application domains reliant on ADC systems, marking a critical milestone in the scientific exploration of noise reduction techniques in analogue circuitry. It drives progress and fosters innovation, offering a promising vision for the future of ADC technology and its broader implications across scientific and engineering disciplines.

FinFET Technology: Modeling and RF Characterization for 5nm Node Technology: A Review

The study offers new methods for understanding and simulating the radiofrequency, analog, and thermal characteristics of the FinFET at the 5nm CMOS technology node. The results of the thermal assessment show that changes in temperature have an effect on the threshold voltage and sub-threshold slope (SS). The maximum oscillation frequency and cut-off frequency of an n-FinFET RF device with a single gate contact are revealed by the RF investigation. Additionally, the study provides information about the device-level temperature sensitivity of the analog and RF Figures of Merit (FoMs) for the 5nm technology. The industry-standard BSIM-CMG model is adjusted to include the effects of self-heating (SH) and parasites in order to improve model accuracy. The updated BSIM-CMG model increases accuracy by taking self-heating and parasite effects into account. Effective heat pathways for lowering junction temperature are found by employing vias on silicon and stacks of conductive materials made of metal. It should be remembered, though, that using these heat pathways could raise parasitic capacitance and negatively impact the circuit's functionality. Keywords: RF Characterization, Thermal Impact, Self-Heating, Figure of Merit, FinFET, Analog Characteristics.

A high-speed MCML charge pump design at 10 GHz frequency in 45 nm CMOS technology for PLL application

A high-speed MCML charge pump design at 10 GHz frequency in 45 nm CMOS technology for PLL application

Design of high performance energy efficient CMOS voltage level shifter for mixed signal circuits applications

In modern integrated circuits (ICs), the near threshold voltage (NTV) regime has gained significant attention due to its potential for enabling energy-efficient and high-performance designs. Voltage level shifters (VLS) play a crucial role in facilitating signal transmission between different voltage domains, ensuring compatibility and reliable operation of ICs. However, the unique challenges posed by near threshold voltage operation necessitate a careful analysis and design of voltage level shifters to mitigate the impact of process variations, supply voltage fluctuations, and other performance limitations. This paper presents, a novel energy efficient voltage level shifter design for NTV regime. We validated the proposed VLS in an industrial 65 nm CMOS technology and ASAP7 7 nm Fin-Fet technology. The post layout parasitic extracted simulations highlight that the proposed VLS, an average improvement of ∼50 %, 37 % and 67 % in propagation delay, power dissipation and layout area, respectively, is obtained over the recently reported VLS design at a VDD = 0.4 V in 65 nm CMOS technology. At ASAP7 7 nm Fin-Fet technology, the proposed design shows an average improvement of ∼52 % and 29 % in propagation delay and power dissipation, respectively over the recently reported VLS design at VDD = 0.3 V. The proposed VLS design offers a compelling solution for achieving high-performance, energy-efficient designs in low-power applications.

A FinFET-based low-power, stable 8T SRAM cell with high yield

Modern battery-enabled systems, such as IoT, require SRAM cells that can maintain data and respond quickly to requests. However, achieving low-power and stable SRAM cells, which are essential for IoT systems, is not possible with CMOS technology due to scaling issues. As a result, new nanoscale devices, such as FinFET, have been introduced as a potential replacement for CMOS in SRAM design. This paper presents a new FinFET-based 8 T SRAM cell with separate reading and writing paths. The cell uses read-decoupling and write-assist pull-down path cut techniques to improve read stability and writability, respectively. Single-ended reading and writing structures reduce power consumption, and stacking transistors, along with read bitline leakage elimination, reduces leakage power dissipation. The proposed cell’s efficiency is evaluated using HSPICE simulator with 10-nm FinFET technology and is compared with conventional 6 T, single-bitline 7 T (SB7T), single-ended 8 T (SE8T), and transmission gate read-decoupled 9 T (TRD9T) SRAM cells at VDD = 0.35 V. The proposed cell improves read stability by 2.59×/1.04 × and enhances writability by 1.38×/1.01 × compared to 6 T/TRD9T and 6 T/SB7T, respectively. It also reduces read power by 28.25 %/19.60 % compared to the 6 T/SB7T and reduces write power by at most 33.40 % and at least 5.46 %. Moreover, the leakage power is reduced by at least 5.80 %. However, the proposed cell increases read/write delay by 1.77×/1.40 × and shows 1.23 × larger layout area compared to 6 T.

Implementation of Taguchi Method in Improving the Logic Gates Performance based on Carbon Nanotube Field Effect Transistor Technology

The International Roadmap for Device and Systems (IRDS) 2022 has emphasized the potential of CNTFETs to replace CMOS technology. Therefore, the substitution of silicon with carbon nanotubes (CNTs) has the potential to open new possibilities for the semiconductor industry, due to their compact size and superior electrical properties. Thus, this project utilized Cadence Virtuoso software to develop an optimized CNTFET design using Taguchi method. In this design, the Taguchi method was implemented to determine the best combination of design parameter and material for optimum CNTFET performance. The design parameter and material that had been chosen were the diameter of carbon nanotube, dielectric material and oxide thickness. The optimized CNTFET model is implemented in circuit study to analyse the propagation delay and power consumption. Five circuits had been designed from the optimized CNTFET which are the inverter, AND, OR, NAND and NOR circuit. The Taguchi Optimization method resulted in significant reductions in the power- delay product (PDP) for all circuits examined, ranging from 7.9954% for the AND circuit to an exceptional 99.9622% for the inverter circuit. These findings highlight the potential for improved power efficiency and faster circuit operation when utilizing the Taguchi Optimization approach.

An Ultra-wideband Low-power Low-noise Amplifier Linearized by Adjusted Derivative Superposition and Feedback Techniques

Ultra-wideband (UWB) applications require low-power and low-noise amplifiers (LNAs) that can operate over a wide frequency range. However, conventional LNAs often suffer from poor linearity and high-power consumption. This research work proposes a novel LNA design that uses the adjusted derivative superposition (DS) technique and feedback to improve the linearity and reduce the power consumption of UWB LNAs. The DS technique enhances the third-order intermodulation (IM3) cancellation by adjusting the bias currents of the transistors, whereas the feedback improves the stability and input matching of the LNA. The LNA is implemented using a degenerated common source topology in a 180 nm standard CMOS technology. The simulation results show that the LNA achieves a power gain of 10–12.2 dB, an input third-order intercept point (IIP3) of about 12 dBm, and a noise figure of less than 2.5 dB over the UWB frequency band of 3.1–10.6 GHz. The input reflection coefficient is less than -10 dB, and the power consumption is 11.6 mW with a 1.5 V power supply. The designed LNA offers a novel and innovative solution for UWB applications that significantly improve the performance and efficiency of UWB LNAs whereas reducing the cost and complexity of implementation.

HfO2-Based Switching Devices with Nitridation of the Bottom Electrode

HfO2 -based Resistive Switching devices are a promising candidate for in-memory computing due to their lowpower consumption, good endurance, reliability, and compatibility with CMOS technology [1]. Controlling theoxygen vacancy (Vo) distribution near the top and bottom electrodes by selecting proper metal-dielectric-metalstack materials has impact on the performance of the device [2-3]. Significant improvement in switching poweris achieved when Vo distribution is higher near the top electrode (TE) and lower near the bottom electrode [4].Introducing nitridation treatment to the TiN bottom electrode shows a significant reduction in switching powerand superior conductance quantization with nanosecond pulse width of programing pulsed operation [5].In this work we studied different TiN bottom electrode (BE) films in the TiN/HZO/TiN MIM toinvestigate its impact of BE TiN on the switching characteristics. Fig. 1 shows schematic for the two differentswitching devices with identical top electrodes (10 nm PVD TiN) and same switching dielectric (10 nm HZO) butwith different N2 levels of 30 nm TiN at the BE. Device-B has higher level of N2 compared to device-A. Formingprocess was performed by applying DC voltage sweep with 1nA compliance current. The device-A has the lowestforming power (0.86nW) as shown in Fig. 2(a). An increase in the forming power consumption was observed fordevice-B (2.45nW) as shown in Fig. 2(b). We carried out the carrier transport characterization at the highresistance state (HRS) prior to forming process. Fig. 2(c)&(d) shows the conduction process in both devices. Indevice-A, the current conduction mechanism followed the hopping conduction in the dielectric as shown in Fig.2(c). The hopping conduction is a bulk-limited conduction mechanism depends on the electrical properties of thedielectric itself such as the trap energy level [6]. The conduction mechanism in device-B (high N2) (Fig. 2(d)) andwas dominated by the Schottky conduction in the HZO layer, which is an electrode-limited conduction thatdepends on the electrical properties at the electrode-dielectric interface [6]. When the active nitrogen atoms areintroduced to the BE, it diffuses to the dielectric due to increased concentration, then connect to the hafnium iondangling bonds as their lone-pair electrons, since the bonding energy of the Hf–N bond is very low (535eV)compared with that of the Hf–O bond (801eV) [7]. This allows a migration of Vo towards TE and reducing the Voconcentration near the BE for device-A leading to carrier hopping. On the other hand, Vo concentration near theBE is completely purged because of high nitrogen concentration (device-B) leading to Schottky conduction. Thisexplains the reduction of forming power in device-A. Fig. 3 shows the resistance distribution after applying 30DC sweeps with reading voltage of 0.1V after each sweep. The device-B (high N2) shows the largest windowbetween HRS and LRS compared to the other devices. That further confirms the forming process in these devices.In summary, low level of N2 reduces the forming power while higher level of N2 enhances the resistance windowbetween LRS and HRS because of Vo concentration variation near BE.

(Invited) Suspended 1D/2D Nanomaterials: Progress on a Waferlevel Technology and Applications

The use of 1D and 2D nanomaterials in emerging electronics and sensor technologies is becoming increasingly important due to their unique properties. Here we would like to highlight a scalable process for suspended nanomaterials that provides additional scope for the development of device properties that can be used in advanced concepts ranging from molecular sensing to quantum applications [1]. For example those applications benefit from arrangements as CNT-based nanoresonators with extremely high quality factors [2] usable for quantum bits with long coherence time [3] or suspended sensing nanomaterials for ultra-low power and extremely sensitive gas sensors [4]. Moreover, straining allows to tune intrinsic physical properties of nanomaterials. Thus, the strain-dependence of the band gap (e.g. CNTs <100meV/% [5], MoS2 ~60meV/% [6],) paves the way for integrated-, highly-efficient-, and tunable light sources for on-chip spectrometry in the context of photonic integrated circuits (PICs), as recently reviewed in [7].Our technological solution to manufacture suspended nanomaterials is aligned with established semiconductor processing chains on 200 mm wafer level and is developed to be modular integrable and compatible with MEMS, MEOMS or CMOS technologies [8]. Along the process chain, we demonstrate wafer-validated deposition processes for semiconducting CNT films which properties can be adjusted with respect to density and even alignment. In particular, for straining aligned CNTs as well as any transferable 2D nanomaterial, we implemented a stressed functional SiO2/SiN layer stack arranged on embedded sacrificial Cu-structures on the wafer surface. After contacting of the nanomaterial and release of sacrificial elements, stressed layers relax, strain and suspend the nanomaterial. This surface engineering approach greatly simplifies the introduction of strain into nanomaterials and makes it accessible for arbitrary device numbers on wafers as well as for monolithic 3D electronic concepts. Unique features include in-plane strains that are applicable in multiaxial directions and can be controlled by designing only two lithography planes. We show that devices with CNTs strained up to 1% determined from Raman spectral analysis, have a positive impact on sensor operation. We show application examples such as a mechanical stress sensor with extremely low on-set sensitivity.

In-Situ Reflectance Absorption Infra-Red Spectroscopy (RAIRS) Study on ALD of HfO2 on TiN and Pt Electrodes

Ferroelectricity in hafnia fluoride analogues has been widely investigated for nonvolatile memory applications. Although ALD of HfO2 technology is enough mature for CMOS technology, hafnia-based ferroelectrics still suffer from major reliability issues such as relaxation, imprint, fatigue, and breakdown.1 These reliability characteristics are thought to be related to the interface conditions between the ferroelectric film and the electrode. Thus, many reports suggested routes to enhance reliability and ferroelectric characteristics by modifying the interface states of the metal-ferroelectric-metal (MFM) capacitors. Unfortunately, only few reports disclose direct observation on evolution of interface formation and its mechanism. Recently, it is reported that scaling down the ferroelectric hafnia-based films to a few nm range dramatically improves the MFM capacitors’ reliability where the series capacitance and surface effect dominate, making it crucial to understand the interface properties carefully.2 In this presentation, we perform In-situ characterization using reflectance absorption infrared spectroscopy (RAIRS) to monitor the surface reaction and interface formation while HfOx ALD using TDMA-Hf with various oxidation reactants, such as H2O, O3, and anhydrous H2O2. TiN and Pt bottom electrodes are investigated at 250 °C. The RAIRS results show that the initial exposure of the oxidant generates the most amount of oxidation on the TiN surface by showing Ti-O and TiN-O peaks which were not observed for the Pt substrate. Moreover, the Ti-O and TiN-O peak area increase versus the dosing time of oxidant was minimum for H2O, and O3 showed continuous peak increase even after 12 s exposure. Interestingly, for the H2O2 case, there was almost no peak increase in the Ti-O bond region like H2O, but the TiN-O and TiO-O peaks appeared after the first 3 s and saturated after 6 s exposure. Also, not only on the TiN substrate, the peak for O-O stretching was observed for the Pt substrate as well, indicating that the H2O2 generates self-limiting peroxide bonds on the surface with a minimum interface formation. This suppressed interface formation with superior film properties using H2O2 might be the reason behind the robust reliability of the H2O2-based HZO capacitor. We are going to report reliability characteristics in conjunction with interface evolution.Acknowledements: We thank to YEST and KEIT for supporting the project through ISTD Program (No.20010806). This work is also supported by GRC-LMD program (task#3001.001) through SRC. The BRUTE hydrogen peroxide was provided by RASIRC. Ozone generator for TMEICReferences 1 J. Mohan et al., ACS AELM, 4, 4 (2022). 2 K. Toprasertpong et al., ACS AMI, 14 (2022).

(Invited) Sequential 3D Integration of Ge Transistors on Si CMOS

In order to keep the scaling progress going is to go 3D. This paper outlines some technology challenges and solutions to integrate Ge p-type MOSFETs sequentially on Si CMOS. Such a solution addresses the grand challenge to enable increased device density. However, the device itself does not have to scale but at the same time innovative solutions are suggested for low supply voltage operation enabling energy efficient integrated circuits (ICs) that will not be dominated by energy consumption in interconnects.By stacking the transistors on top of each other, and connect them with inter-tier via, the density of transistors per unit area increases. This approach demands that transistors are fabricated at a lower temperature compared to today’s Si CMOS technology. Therefore, we have focused on Ge based transistors, which has an inherently lower process temperature compared to Si transistors.In this paper several technological and design breakthroughs towards realizing Ge based sequential 3D circuits will be shown. We will present: A process to realize thin single crystalline Ge layers on planarized wafers with metal layers in lower tiers.A gate dielectric stack (Ge/Si/TmSiO/Tm2O3/HfO2/TiN) on Ge that enables adequately low defect densities at the dielectric/Ge interface allowing predictable and reliable Ge transistorsFully depleted Ge pFET devices fabricated at a low temperature compatible with sequential 3D. The devices exhibits 60% higher mobility compared to reference Si devices.3D digital circuits with pFETs on top of nFETs can enable area reduction by 30-50% depending on cell type.3D standard cells with lower parasitic capacitance (~30%) compared to 2D cells, enabling lower dynamic power consumption and more energy efficient integrated circuits.

Design and Performance Analysis of a [8/8/8] Charge Domain Mixed-Signal Multiply-Accumulator

This article describes the design and performance analysis of a charge domain mixed-signal multiply-accumulator (MAC) using RDAC, CDAC, and SAR-ADC with an 8-bit resolution for input, weight, and output. The arithmetic accuracy is mainly determined by the ADC, and the gain error has a significant impact. The mismatches and thermal noises of the RDAC and the CDAC are averaged by the number of multiply-accumulate units m connected to one ADC. As a result, if m is large enough, mismatches and thermal noises have a limited impact on the computation accuracy. Most of the computational energy is determined by the energy consumed by the SAR-ADC, and the computational energy per operation can be reduced by increasing m. This last metric is mainly determined by the charge and discharge energy of the CDAC for sufficiently large m values. Furthermore, since RDAC consumes energy unnecessarily, the turn-off timing of RDAC should be optimized. These MAC units have been designed and prototyped using 28 nm CMOS technology, integrating 12,288 arithmetic units while operating at 180 MHz, resulting in an arithmetic speed of 4.4 TOPS. The r-MVM accuracy is about 1% and a high energy efficiency of 240 TOPS/W as a MAC macro and 64.4 TOPS/W as a system has been achieved.

Dual-tuned high-swing variable-gain amplifier with enhanced dB-linear control

In this work, an analog-controlled variable gain amplifier (VGA) is proposed that demonstrates high linearity across a wide range of control voltages and low noise for analog front-end receivers. This work presents a dual-tuning technique utilizing diode-connected P-MOS load and pseudo-exponential approximation based source degeneration (DCPL-PESD), which enables simultaneous tuning of different control voltages to achieve the required dB-linear characteristic. The gain is increased by cross-coupling the input transistors of the differential pair. To extend the gain range, three single-stage VGAs are cascaded. The design and implementation of this VGA were carried out using the Cadence Virtuoso tool in 180 nm CMOS technology. Post-layout results indicate that the 3-stage cascaded VGA offers a gain range of 67.5 dB, of which 55 dB is dB-linear. By tuning the control voltage VC, it provides a continuous 18 dB dB-linear gain. The overall VGA consumes 0.232 mA from a 1.8 V power supply, with a power consumption of 417 μW. The bandwidth of 3-stage VGAs is measured as 46 MHz. The minimum input-referred noise (IRN) of this VGA is 4.158 nVHz. The total area, including the bias circuit and buffer, is 0.0054 mm2, and the output 1 dB compression point is −2.83 dBm at the gain of −1 dB.