CMOS Switches Research Articles

(Invited) Atom Switch Technology for Low-Power Nonvolatile Logic Application

This paper reports Atom switch technology featuring Cu nanometer-scale conducting bridge in a solid-electrolyte. The switch exhibits resistance-switching, which is originated from Cu electrolysis through the solid-electrolyte. Three types of device structure of Atom switches such as two-terminal device, CAS and DCAS are reviewed with the object of the routing switch application to directly replace the conventional CMOS switch element, realizing the low-power, nonvolatile programmable logic.

Magnetic Properties of Spin Quantum Cross Devices Utilizing Stray Magnetic Fields

ABSTRACTWe investigate structural and magnetic properties of Co thin-film electrodes used in a new type of spin quantum cross (SQC) devices, in which a strong stray magnetic field could be generated between the both edges of magnetic thin-film electrodes. We also calculate the stray field between the two edges of Co thin-film electrodes in SQC devices and discuss the possibility to novel spintronics devices. As a result of magnetic force microscopy (MFM) observations, the stray fields are generated from the Co edges, and they are uniformly distributed. This result indicates that magnetic single-domain structures can be formed. This is consistent with the result obtained by magneto-optical Kerr effect (MOKE). The theoretical calculation reveals that the stray field exhibits as high as 7000 Oe under the condition that the distance between the two Co edges is 5 nm and the Co thickness is 19 nm. These results indicate that SQC devices utilizing stray fields can be expected as novel spintronics devices, such as spin filtering devices and beyond CMOS switching devices.

A 20b Clockless DAC With Sub-ppm INL, 7.5 nV/√Hz Noise and 0.05 ppm/°C Stability

This paper presents a 20b clockless DAC designed for precision calibrated systems. The architecture is a 6b parallel resistor voltage divider with a 14b R-2R subDAC. This architecture is inherently good for noise and temperature stability. Major causes of nonlinearity are discussed. A single current-output calibration DAC corrects for both random resistor mismatch and systematic resistor nonlinearity. A force and sense switch topology overcomes INL from CMOS switch resistance. The DAC is implemented in a 0.6 μm 30 V BiCMOS process with 5 V CMOS devices and Si-Cr thin-film resistors. It achieves 0.33 ppm INL and 7.5 nV/√Hz noise with a ±10 V output span. It has 0.05 ppm/°C temperature stability and settles in 1 μs. Current consumption is 4.2 mA from 30 V supplies, excluding power required for external reference buffers.

A 4th-order Switch-capacitor Low-pass Filter for Quartz Gyroscope Interface Circuit

This paper presents the computer aided design of a 4th-order switch-capacitor low-pass filter applied in quartz gyroscope interface circuit. After a introduction of switch-capacitor filter (SCF) and its application in quartz gyroscope, the system-level analysis and design is given. Then the circuit design of amplifier, CMOS switch and non-overlapping clock is described. The Fourth-order low-pass SCF has been implemented under 0.5um CMOS process and simulated in computer aided design software. The final simulation results show that the passband is 99.7Hz , and the maximum pass-band ripple is about 0.14dB.The stop-band is 1KHz, and the minimum stop-band attenuation is 78.6dB. DOI: http://dx.doi.org/10.11591/telkomnika.v11i10.3398

A low-power 20 GSps track-and-hold amplifier in 0.18 μm SiGe BiCMOS technology

An open-loop 20 GSps track-and-hold amplifier (THA) using fully-differential architecture to mitigate common-mode noise and suppress even-order harmonics is presented. CMOS switch and dummy switches are adopted to achieve high speed and good linearity. A cross-coupled pair is used in the input buffer to suppress the charge injection and clock feedthrough. Both the input and output buffers use an active inductor load to achieve high signal bandwidth. The THA is realized with 0.18 μm SiGe BiCMOS technology using only CMOS devices at a 1.8 V voltage supply and with a core area of 0.024 mm2. The measurement results show that the SFDR is 32.4 dB with a 4 GHz sine wave input at a 20 GSps sampling rate, and the third harmonic distortion is −48 dBc. The effective resolution bandwidth of the THA is 12 GHz and the figure of merit is only 0.028 mW/GHz.

(Invited) Opportunities and Challenges of Atom Switch for Low-Power Programmable Logic

Opportunities and challenges of atom switch featuring Cunanometer-scale conducting bridge in the solid-electrolyte arediscussed with comparing the other emerging memories. Atomswitch having the high on/off conductance ratio is suitable todirectly replace the conventional CMOS switch element, realizingthe low-power, nonvolatile programmable logic. Reliabilitychallenges of the atom switch are also discussed in the view pointof the stabilization of the on- and off-states.

Analysis of the effect of stray capacitance on a charge/discharge-based electrical capacitance tomography system

The measurement circuit of electrical capacitance tomography (ECT) system mainly includes CMOS switches, C/V conversion circuit and Data processing circuit. In order to improve the image reconstruction quality, conversion circuit is very necessary to the small capacitance measurement circuit. A charge/discharge measurement circuit is one of the most suitable for the C/V conversion circuit in ECT. The stray capacitance between the measurement electrodes and earth can be large and have an effect on the capacitance measurement. This paper analyzes this effect, taking into account the ON-resistance of the COMS switch, the unit gain frequency of op-amp, and gain error in the measurement circuit. Finally, it is shown that if the range of stray capacitance is 150±60pF, overall error would be estimated. Comparing the effects of the circuit parameters, this charge/discharge-based capacitance is effectively stray-immune. It is a more efficient analysis to C/V circuit in ECT and offers a great benefit to information processing.

A Fully Differential Chopper Circuit in 130nm CMOS for Noise Minimization in Sensor Applications

For sensor applications, the bandwidth of interest is generally a few hertz. In this bandwidth, offset and 1/f noise are the dominant sources of error. Chopping technique is an efficient approach to decrease the 1/f noise and low-frequency offset of CMOS amplifiers; thus, in this paper, a proposed chopper circuit to tackle these problems is presented. The chopper circuit is designed using complementary CMOS switches that are optimized to achieve symmetric linear resistance in the range of input signal. The proposed circuit has a low ON resistance that only varies within 8% of its value for a rail to rail input. To validate its operation, it is used to build up a fully differential chopper stabilized CMOS amplifier powered at 1V. The resulting circuit achieves a thermal noise floor of 10 nV/√Hz and reduces the input referred noise corner frequency from 1-kHz to300mHz.

Analysis of parasitic effects in triple‐well CMOS SPDT switch

A comparison between a conventional body floating single pole double throw (SPDT) CMOS switch design and a proposed switched gate floating CMOS SPDT switch design based on an analysis of parasitic effects is presented. In standard CMOS technology, the switched gate floating switch is analytically proved to have higher isolation owing to the alleviation of parasitic diode and substrate coupling effects in the operation state. The proposed switch maintains a similar insertion loss as conventional swithches while achieving an average of 6 dB isolation improvement over the operating frequency, which agrees well with the presented analysis.

DP4T RF CMOS Switch: A Better Option to Replace the SPDT Switch and DPDT Switch

In this paper we have explored the design of double-pole four-throw (DP4T) RF CMOS switch at 45-nm technology and analyzed the better drain current and switching speed as compared to the existing single-pole double-throw (SPDT) switch and double-pole double-throw (DPDT) switch. For the proposed DP4T RF CMOS switch results the peak output currents around 0.387 mA and switching speed of 36 ps. We are using the CMOS inverter propertied to some extent to design this DP4T switch. This article deals with the evolution of RF switches and its design through reviewing available patents and introduces the latest applications of proposed switch. Keywords: DP4T switch, RF CMOS switch, single-gate MOSEFT, VLSI

Ultra-High Density Content Addressable Memory Based on Current Induced Domain Wall Motion in Magnetic Track

A new path to frame low power, high-density and fast integrated circuits has been rolled out by the observation of current-induced domain wall (DW) motion in magnetic track. As an advanced extension of this mechanism, high performance racetrack memory can be built up combining with magnetic tunnel junction (MTJ) read and write heads. The rapid progress of CoFeB/MgO perpendicular magnetic anisotropy (PMA) shows that the PMA MTJ can be scaled down to 20 nm while keeping fast data access. These recent discoveries allow us to design an ultra-high density content addressable memory (CAM), one of the most important applications of MRAM. The mainstream CAMs suffer from high power and large area as its conventional structure is composed of numerous large-capacity SRAM blocks in order to provide fast data access. MRAM based non-volatile CAMs have been proposed to relive the power consumption, however the density issue cannot be surmounted due to the large switching currents. In this paper, we present a design of NOR-type CAM based on DW motion in PMA magnetic tracks. The CMOS switching and sensing circuits are globally shared to optimize the cell area down to 6 F2/bit; the complementary dual track allows the local sensing and faster data search speed while keeping low power. By using an accuracy spice model of PMA racetrack memory and CMOS 65 nm design-kit, mixed simulations have been performed to demonstrate its functionality and evaluate its high performance.

Impact of Injected Charges, Clock Noise and Operational Amplifier Imperfections on the Sample and Hold (SH) Overall Performance

The growing use of digital processing in analog environments underlines the importance of Analog Digital Converter (ADC) occurrence in circuitry. The quality and reliability of the conversion are closely linked to the Sample and Hold (SH) performance. Actually SH is a key component in the Analog/Digital chain. The Operational Amplifier being at the heart of the SH influences its output and subsequently impacts the reliability and quality of the conversion. In this paper we present the impact of both Operational Amplifier intrinsic characteristics and external factors such as injected charges, and clock noise on the SH overall performance. We limit our consideration to the offset and parasite capacities as the only relevant Operational Amplifier intrinsic characteristics. We’ll introduce the Operational Amplifier and SH functional characteristics then address the impact of each of these parameters on the SH output which the ADC works on. A behavioral description of the Operational Amplifier based on the Verilog-A language under Cadence approach is used. Furthermore a behavioral/analog mixed description is considered for the SH: the Operational Amplifier described behaviorally in Verilog-A is associated to analog components in Cadence libraries and CMOS switches act as SH. However this simplistic approach doesn’t reflect all the challenges involved, because it is not enough to connect a SH to ADC to flawlessly digitalize an analog signal. The SH architecture and the Operational Amplifier characteristics play also a role for a reliable sampling and therefore a good quality conversion prospect.In this study the SH performance is evaluated through its non-linearity which in turn determines the sampling accuracy a key factor for a conversion. This study is as shown that small amplitude signals are more sensible to sampling errors related to Operational Amplifier offset. Furthermore the stray capacities attenuate the SH signal output. The injected charges and the clocknoise as strongly interrelated contribute to the non-linearity of the conversion chain.

ANALYSIS OF DRAIN CURRENT AND SWITCHING SPEED FOR SPDT SWITCH AND DPDT SWITCH WITH THE PROPOSED DP4T RF CMOS SWITCH

Conventional CMOS switch uses NMOS as transistors in its main architecture requiring a control voltage of 5.0 V and a large resistance at the receivers and antennas (ANTs) to detect the signal. A CMOS integrated circuit switch uses FET transistors to achieve switching between multiple paths, because of its high value of control voltage. Hence it is not suitable for modern portable devices which demand lesser power consumption. Therefore, we proposed a new Double-Pole Four-Throw (DP4T) switch by using RF CMOS technology and analyzed its performance. Further, main objective is to provide a plurality of such switches arranged in a densely configured switch array, where the power and area could be reduced as compared to already existing switch configuration as SPDT and Double-Pole Double-Throw (DPDT) transceiver switches, which is simply a reduction of signal strength during transmission of the RF signals. The presented result for the proposed DP4T switch reveals the peak output currents (drain current) around 0.116–0.387 mA and a switching speed of 19–36 ps.

A Fully-Integrated Efficient CMOS Inverse Class-D Power Amplifier for Digital Polar Transmitters

In this work, we have demonstrated a fully-integrated, high-efficiency CMOS inverse Class-D PA. Such efficient switching amplifiers can form the core of mixed-signal polar transmitters. A comprehensive analytical framework has been developed to determine optimum component values to maximize efficiency. Operating from a 1-V supply, the PA achieves a peak efficiency of 44% without any RF process options. This is comparable to that of state-of-the-art CMOS switching PAs despite using a much simpler output matching network.

HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures

Dual supply voltage design is widely accepted as an effective way to reduce the power consumption of CMOS circuits. In this paper, we propose a comprehensive design framework that includes dual- scheduling, dual- allocation, controller synthesis as well as layout generation. In particular, we address a problem of high-level synthesis with objective of minimizing power consumption of storage units and multiplexers using dual- ; this is made possible by utilizing timing slack that is left in the data-path after operation scheduling. We use integer linear programming (ILP) and also provide heuristic algorithms to solve the dual- register and connection allocation. The physical layout of dual-circuits has to separate power rails of and cells from each other. We propose a voltage island based placement algorithm to relieve this restriction and allow more flexibility of placement. In experiments on benchmark designs implemented in 1.08 V (with Vddl of 0.8 V) 65-nm CMOS technology, both switching and leakage power are reduced by 20% on average, respectively, compared to data-path with dual-Vdd applied to functional units alone. Detailed analysis of area and wirelength is performed to assess feasibility of the proposed method.

Design of a Tri-Modal Multi-Threshold CMOS Switch With Application to Data Retentive Power Gating

A tri-modal multi-threshold CMOS (MTCMOS) switch design is presented. Similar to the conventional MTCMOS switches, the tri-modal switch comes in two flavors: header and footer. The tri-modal switch provides three different power modes for the underlying circuit: active, drowsy, and sleep. The ability of data retention in the drowsy mode makes the proposed tri-modal switch an excellent candidate for implementing data-retentive power gating designs. We will see that three different low-power design schemes, namely data-retentive power gating, multi-drowsy mode structures, and on-chip dynamic voltage scaling, are implemented using the proposed tri-modal switch. We show that our proposal introduces superior low-power solutions across various circuit operating modes using a single circuitry.

Optimization of Drain Current and Voltage Characteristics for DP4T Double-Gate RF CMOS Switch at 45-nm Technology

Independent gate control in double-gate devices enhances the circuit performance and robustness while substantially reducing leakage and chip area. In this paper, we have explored the circuit techniques for a DP4T RF CMOS switch, which is an application of the independent double-gate MOSFET with symmetrical gate at 45-nm technology design and analyzed the better drain current, output voltage, ON resistance, ON/OFF ratio and insertion loss for the DP4T DG RF CMOS switch.

Highly Integrated and Tunable RF Front Ends for Reconfigurable Multiband Transceivers: A Tutorial

Architectural and circuit techniques to integrate the RF front end passive components, namely the SAW filters and duplexers that are traditionally implemented off chip, are presented. Intended for software-defined and cognitive radio platforms, tunable high-Q filters realized by CMOS switches and linear or MOS capacitors allow the integration of highly reconfigurable transceiver front ends that are robust to in-band and out-of-band blockers. Furthermore, duplexer techniques based on electrical balance concepts are introduced to enable highly integrated and programmable radios for full-duplex applications such as 3/4G transceivers. Several case studies are presented that offer highly linear and low-noise transceiver front ends that satisfy the challenging requirements of cellular standards, yet offer considerably lower cost and size compared to the state-of-the-art transceivers available today.

Design of Integrated Dual-Loop $\Delta$ –$\Sigma$ Modulated Switching Power Converter for Adaptive Wireless Powering in Biomedical Implants

This paper presents an integrated CMOS switching power converter that accommodates adaptive wireless powering scheme in biomedical implants. It employs the techniques of dual-loop error correction, observation-based oversampling, and Δ- Σ modulation to enhance transient response, line/load regulation, and noise suppression performance. By adopting a digital filter for proportional-derivative compensation, fully on-chip frequency compensation is achieved. In addition, a double sampling technique is introduced to improve the signal processing speed. The converter was designed and fabricated with a 130-nm CMOS process. The measurement results demonstrate 23.2/20.4-μs up-/down-tracking times to full-range reference voltage step changes. A 28.5-mV/V line regulation is achieved, when the supply voltage varies from 1.15 to 1.50 V. In addition, with a 1.20-V supply, the converter responds to a 10%-to-100% load current step change within 22.1 μs. A maximum efficiency of 95.5% is measured at 0.90-V output voltage and 45-mW output power. Noise power spectrum demonstrates a 100-dB signal-to-noise ratio in the converter.

A novel low-offset dynamic comparator for sub-1-V pipeline ADCs

A novel low-offset dynamic comparator for high-speed low-voltage analog-to-digital converters (ADCs) has been proposed. In the proposed comparator, a CMOS switch takes the place of the dynamic current sources in the differential comparator, which allows the differential input transistors still to operate in the saturation region at the comparing time. This gives the proposed comparator a low offset as the differential comparator while tolerating a sub-1-V supply voltage. Additionally, it also features a larger input swing, less sensitivity to common mode voltage, and a simple relationship between the input and reference voltage. This proposed comparator with two traditional comparators has been realized by SMIC 0.13 μm CMOS technology. The contrast experimental results verify these advantages over conventional comparators. It has been used in a 12-bit 100-MS/s pipeline ADC.