CMOS Process Technology Research Articles

A configurable area-efficient LCoS chip design with centrosymmetric pixel array

Liquid Crystal on Silicon (LCOS) is a microdisplay technology that combines CMOS tech with integrated circuit design and liquid crystal technology. In this paper, the proposed LCOS backplane can greatly reduce size of the pixel pitch. In order to reduce the size of the pixel pitch, a digital pixel driver scheme and a new layout design are shown. The proposed LCOS with digital pixel driver scheme was fabricated using 0.18 um CMOS process technology and the simulation image have shown the correct results. The pixel size is 3 um× 6 um in this design and the area of pixel array with the resolution of 1632 × 1632 is 10127 um × 5060 um.

Novel Voltage-Mode PID Controller Using a Single CCTA and All Grounded Passive Components

A compact voltage-mode proportional-integral-derivative (PID) controller based on the utilization of a single current conveyor transconductance amplifier (CCTA) is presented in this paper. The presented active PID controller is made up of a single CCTA, and four truly grounded passive components, i.e. two resistors, and two capacitors. The design consideration of the controller parameters has been examined. Besides, the crucial sensitivity performances of the controller parameters for ideal and non-ideal conditions have also been discussed. An application on the closed-loop test system is demonstrated to validate the practicability of the proposed PID controller circuit. To confirm the theoretical behavior, the proposed circuit is simulated with the PSPICE program using TSMC 0.35-um CMOS process technology. Experimental test results based on commercially available CFOA AD844 and OTA CA3080 integrated circuits are also provided to demonstrate the practicality of the proposed circuit.

A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS

This paper presents a low-power, high-bandwidth wireline transceiver for chiplet. The transceiver uses a new technology of correlated non-return to zero (CNRZ) to improve the pin efficiency and reduce the noise of the common mode and crosstalk (CMN and XTALK). The transmitter adopts a 4:1 multiplexer (MUX) and a special voltage-mode driver [source series terminated (SST)] to improve the power efficiency. The receiver utilizes a low jitter clock-and-data alignment (CDA) based on high resolution phase interpolator (PI) and a MINI-PLL with differential filter based to improve the jitter performance of the receiver’s clock. In addition, a special continuous-time linear equalizer (CTLE) is introduced into the multiple-input compare (MIC) based decode circuit to reduce the receiver’s bit error rate (BER). This transceiver is designed with a 28 nm CMOS process technology and supplied with 0.9/1.2 V. Simulation results show that this transceiver can operate at 200 Gb/s with the 33.3 Gb/s single-wire data rate and a power consumption of 1.06 pJ/b. The transceiver’s BER is less than 1E-15 and eye-wide-opening is 12.02 ps (48.08% UI), which is under 10 dB channel loss at 20 GHz Nyquist frequency.

Compact Low-dropout Linear Regulator Design in 0.13 µm CMOS Technology for IoT Based Remote Infectious Disease Monitoring System

With the widespread adoption of the internet of things (IoT), power management of the different electronic (i.e. IoT) devices has become a major challenge. The low-dropout linear regulator (LDO) circuit is widely used for power management applications of electronic devices. This article reports the design and simulation of a low-dropout linear regulator (LDO) circuit, powered by a 1.2 V DC power supply voltage. In order to optimise the power dissipation, low layout silicon area and lower dropout voltage, a current mirror based transistor optimised LDO circuit has been implemented. The simulation results show that the proposed LDO regulator circuit exhibits a 582 mV low-dropout voltage, 1.568 mW power dissipation, and a very compact layout silicon area of 163.84 µm 2(12.795 × 12.805 µm). The proposed LDO linear regulator archi- tecture is designed and validated in 0.13 µm TSMC CMOS process technology using Mentor Graphic EDA tools.

An energy-efficient single-cycle RV32I microprocessor for edge computing applications

With the advancement in the Internet of Things (IoT) and Wireless Sensor Node (WSN) applications computation on edge is preferred over computation on the cloud. However, due to limited resource availability in the edge environment, energy efficiency can be seen as the primary barrier in the growth of edge computing devices. In edge computing applications like wearable devices, forest monitoring systems, and other such applications, power is of utmost importance. The use of a complex, pipelined, general-purpose processor is redundant for such low-end applications and it leads to high power consumption. Hence, edge computing systems require low-power solutions while still maintaining a minimum performance level. In this work, an energy-efficient single-cycle RISC-V instruction set architecture (ISA) based RV32I processor is designed for low-end edge computing applications. The design incorporates base integer implementation of RISC-V ISA. The proposed computing system is designed using Verilog HDL and synthesized on Semi-conductor Laboratory (SCL) 180 nm CMOS process technology node. The synthesis tool reports power consumption of 14.7 mW at 50 MHz frequency with an area of 0.24 mm2. Though synthesis of this design reports area of 0.24 mm2, the design is taped out as a part of an available shuttle project where die size is fixed to 5 mm × 5 mm. The PNR (Place and Route) tool reports power consumption of 11.8 mW at an operating frequency of 40 MHz. A basic functional testing of proposed fabricated RV32I chip is carried out in laboratory experimental setup and results are presented. The comparison result shows that the proposed RV32I processor consumes 0.29 mW/MHz power which is less than state-of-the-art low-end processors. Hence, the proposed design is suitable for low-end edge computing applications.

Digital Image Blending by Inexact Multiplication

Digital image blending is commonly used in applications such as photo editing and computer graphics where two images are combined to produce a desired blended image. Digital images can be blended by addition or multiplication, and usually exact addition or multiplication is performed for image blending. In this paper, we evaluate the usefulness of inexact multiplication for digital image blending. Towards this, we describe how an exact array multiplier can be made inexact by introducing vertical cut(s) in it and assigning distinct combinations of binary values to the dangling inputs and product bits. We considered many 8-bit digital images for blending and the blended images obtained using exact and inexact multipliers are shown, which demonstrates the usefulness of inexact multiplication for image blending. For 8 × 8 image blending, one of our inexact array multipliers viz. IAM01-VC8 was found to achieve 63.3% reduction in area, 21% reduction in critical path delay, 72.3% reduction in power dissipation, and 78.1% reduction in energy compared to the exact array multiplier. In addition, IAM01-VC8 achieved 60.6% reduction in area, 9.7% reduction in critical path delay, 64.7% reduction in power dissipation, and 68.1% reduction in energy compared to the high-speed exact 8 × 8 multiplier that was automatically synthesized using a logic synthesis tool. The exact and inexact multipliers were physically realized using 32/28 nm CMOS process technology.

A compact sub-Hertz local field potential amplifier for implantable biomedical devices

Local field potentials (LFPs) are the ensemble of low frequency neural signals recorded invasively via microelectrodes implanted into brain tissues. The LFP signals acquired by micro-electrodes are very small in amplitude, typically in the range of 1 μV to 0.5 mV, depending on the distance from the electrode and on the size of a cell and contain the signal energy below 1 Hz. These weak signals are required to be amplified by an analog front-end amplifier. In this paper, the design methodology of a local field potential amplifier for an implantable neural recording system is presented. The LFP amplifier is implemented through a low power, low noise front-end instrumentation amplifier. In order to suppress large electrode-induced DC offset voltages, a modified pseudo-resistor is employed in the amplifier’s feedback. The enlarged resistance offered by the pseudo resistor realizes a high-pass cut-off frequency which is well suited for capturing the neural signals occurring in the sub-Hertz frequency range. As a case study, the instrumentation amplifier featuring modified pseudo resistor configured for LFP recording applications is fabricated in a standard 0.18μm CMOS process technology. The measurement results show the proposed LFP amplifier has a low-pass corner frequency of 300 Hz and achieves a high-pass corner frequency of 0.009 Hz with a maximum gain of 37 dB. The LFP circuit fully integrated on-chip occupies an active area of 0.056 mm2 and a power consumption of 1.8 μW from a 1.5-V supply.

Design and Analysis of SRAM Cell for Smart Application

In today's circuittechnology, power consumption and savings are key concerns. The driving reasonsbehind these innovations are portable devices that require high throughput andlow power dissipation, such as computers, phones, and Personal DigitalAssistants (PDAs). In portable devices, reducing or decreasing IC dissipatedpower through design optimization is a big problem, and restricted batterylifespan places very severe restrictions on overall power usage. In this study SRAMcircuit for smart applications has been investigated using various factors suchas write, read, dynamic, static power with voltage and temperature. The powerconsumption analysis is the most essential criteria for memory design. Becausedata stability is a critical concern, affecting both the read and write operations.The implemented 9T SRAM in this study is more efficient than the other SRAM interms of power usage. When compared with the existing SRAM circuits taken forcomparison of different parameters, the proposed 9T SRAM, circuit uses lessthan 28.2% write power, while it uses about the same for read operation. Thedata retention voltage for both circuits is 0.29 V, which is utilized to storethe data in the circuit. The 32 nm Bulk CMOS process technology from PTM filesis used for designing and analysis.

Low voltage EX-CCCII based on quasi-floating gate technique and its application as precision rectifier

This paper introduces a novel low-voltage low-power Extra-X Current Controlled Current Conveyor (EX-CCCII) based on quasi floating gate (QFG) MOSFET. The QFG technique is employed in low voltage applications and overcomes the limitation of the floating gate technique. The presented circuit is implemented at a supply voltage of ±0.5 V with a power consumption of 90 µW at 20 µA bias current. As an application, the proposed QFG based EX-CCCII is employed to realize a novel current mode precision rectifier circuit. This circuit can simultaneously provide positive and negative type half wave and full wave rectifiers with the same circuit configuration. Furthermore, the rectifier circuit has low input and high output impedance terminals making it suitable for cascading with other current mode circuits. All the results provided to verify the circuit performance are simulated using CADENCE VIRTUOSO SPECTRE simulator with 0.18 µm UMC CMOS technology process parameters. The simulation results confirm the theoretical concept.

Voltage mode and trans-admittance mode first-order universal filters employing DV-EXCCCII

ABSTRACT This paper reports a first-order voltage mode and trans-admittance mode universal filter from the same circuit structure. This configuration employs a single Differential Voltage Extra-X Current Controlled Current Conveyor (DV-EXCCCII) and one capacitor to realise a first-order Low Pass Filter (LPF), High Pass Filter (HPF), and All Pass Filter (APF) in voltage mode and trans-admittance mode. The DV-EXCCCII is an electronically tunable analog block, so the filter response can be varied with the bias current of the DV-EXCCCII. No matching constraints are necessary to realise the proposed filter. The sensitivity is found to be low because of passive components and also due to non-idealities. The reported circuit configuration is implemented through CADENCE VIRTUOSO and verified in SPECTRE using 0.18 µm UMC CMOS technology process parameters.

An On-Chip Planar Inverted-F Antenna at 38 GHz for 5G Communication Applications

This paper presents an on-chip planar inverted-F antenna (PIFA) implemented in TSMC 180 nm CMOS process technology. The antenna operates at a 5 G millimeter-wave center frequency of 38 GHz. The ultrathick metal (UTM) layer of the technology is utilized to implement the on-chip antenna (OCA). The OCA is positioned close to the edge of the microchip for improving the gain performance of the antenna. The open end of the antenna is folded to develop a top-loaded PIFA structure yielding better 50 Ω impedance matching and wider bandwidth. On-wafer measurements are conducted through the Cascade Microtech Summit 11K probe-station and ZVA-50 vector network analyzer to measure the return loss and gain of the fabricated on-chip antenna. The measurements are performed after placing the fabricated OCA over a 3D-printed plastic slab to minimize the reflections from the metallic chuck of the probe station. The measurement results show that the fabricated on-chip PIFA achieves a minimum return loss of 14.8 dB and a gain of 0.7 dBi at the center frequency of 38 GHz. To the best of the authors’ knowledge, the presented OCA is the first on-chip PIFA designed, fabricated, and tested at the 5G millimeter-wave frequency of 38 GHz.

Theoretical and Experimental Investigation of a Photoelectric-Thermoelectric Integrated Power Generator Filled by Al Layer

This article presents the theoretical and experimental investigations of a novel integrated power generator. A solar cell and a thermoelectric generator (TEG) are integrated in a single chip. The fabrication process of the integrated power generator is compatible with the CMOS process and microelectromechanical system (MEMS) technology. Hence, the TEG and the solar cell can collect luminous energy and thermal energy at the same time. The TEG consists of n-type and p-type thermal legs, which are connected in squares and can supply a dc voltage. By experimental measurements, when the TEG is covered by an aluminum layer, its voltage factor and power factor are 0.149 V/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> K and 3.03 nW/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> K <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , respectively. The performance is better than the chip filled by thermal grease. In addition, the solar cell consists of several p-n junctions, which are formed by doping on the silicon substrate. Both the top and back of the solar cell can receive light. When light is incident on the top and bottom surfaces of the chip, the conversion efficiencies of the photoelectric generator are 4.45% and 0.682%, respectively.

CMOS Trans Conductance based Instrumentation Amplifier for Various Biomedical Signal Analysis

Feed forward design techniques for the Trans-conductance operational amplifier removes the barriers of operating frequencies. It is now possible to design amplifiers with large the Trans-conductance that operates at Giga hertz frequency range. There are several Trans-conductance amplifiers used to design a medical and Industrial application that helps in processing various bio medical signals such as Electrocardiographs, Electroencephalographs, Electromyograms and several others. The proposed paper shows the implementation of an instrumentation amplifier using CMOS based the Trans-conductance operational amplifiers also the processing of biomedical ECG, EEG and EMG signals. The CMOS process technology helps to integrate complex circuits on minimal surface area. The Trans-conductance instrumentation operational amplifiers has features includes noise reduction, low DC offset, High output impedance and Common Mode rejection Ratio values. The circuit implementation and simulations has been done on Electronic Design and Automation tool with 0.13μm CMOS process technology.

Wireless Photometry Prototype for Tri-Color Excitation and Multi-Region Recording.

Visualizing neuronal activation and neurotransmitter release by using fluorescent sensors is increasingly popular. The main drawback of contemporary multi-color or multi-region fiber photometry systems is the tethered structure that prevents the free movement of the animals. Although wireless photometry devices exist, a review of literature has shown that these devices can only optically stimulate or excite with a single wavelength simultaneously, and the lifetime of the battery is short. To tackle this limitation, we present a prototype for implementing a fully wireless photometry system with multi-color and multi-region functions. This paper introduces an integrated circuit (IC) prototype fabricated in TSMC 180 nm CMOS process technology. The prototype includes 3-channel optical excitation, 2-channel optical recording, wireless power transfer, and wireless data telemetry blocks. The recording front end has an average gain of 107 dB and consumes 620 of power. The light-emitting diode (LED) driver block provides a peak current of 20 mA for optical excitation. The rectifier, the core of the wireless power transmission, operates with 63% power conversion efficiency at 13.56 MHz and a maximum of 87% at 2 MHz. The system is validated in a laboratory bench test environment and compared with state-of-the-art technologies. The optical excitation and recording front end and the wireless power transfer circuit evaluated in this paper will form the basis for a future miniaturized final device with a shank that can be used in in vivo experiments.

Total ionizing dose effect on 2-D array data transfer ICs designed and fabricated by 0.18 μm CMOS technology

Circuits for CMOS two-dimensional (2-D) array data transfer are indispensable for applications such as space and nuclear fields. Issues include being operated with higher speed, lower power, fewer size penalties, and radiation hardness. To meet these requirements, two kinds of CMOS 2-D array data transfer circuits, such as a shift register type and a memory access type, are proposed and fabricated by the standard 0.18 μm CMOS process technology. In both types, 16 μm pitch, 8 × 128 array data transfer operations were realized with a data rate of more than 1 Gb/s. Furthermore, we conducted 60Co γ-ray irradiation experiments on those circuits. The current consumption ratio of the shift register type to the memory access type ranges from 150 to 200% as the dosage increases. The result indicates that the memory access type has better radiation hardness at 1 Gb/s than that of the shift register type.

Design and simulation of differential transimpedance amplifier with active feedback for optical receivers

AbstractAn active feedback network‐based bandwidth extension technique for CMOS differential transimpedance amplifier (TIA) is proposed in 0.18 µm CMOS process technology. The design consists of three stages in differential mode. The first stage is a common‐source amplifier that minimizes noise. A common collector stage is used for level shifting and buffering in the second stage. The third stage is a differential amplifier that provides additional gain. In addition to these three stages, an active CMOS negative feedback circuit is used for extending the bandwidth. The proposed design achieves a gain of 45.2 dBΩ with a 3 dB bandwidth of 21.23 GHz. The active feedback circuit provides an additional bandwidth of 7.3 GHz. The TIA achieves a data rate of 30 Gb/s with input‐referred noise current density of 63.1 pA/ and jitter of 9.07 ps. The TIA consumes a power of 10.3 mW with a supply voltage of 1.8 V.

A 60‐GHz low‐noise amplifier with +7.258‐dBm third‐order input intercept point using current reuse feedforward distortion cancellation for 5G emerging communication

AbstractIn the ever‐growing 5G technology, the millimetre‐wave (mmWave) frequency spectrum is the inevitable mainstream for high‐speed wireless communication. The wide‐ranging spectrum bandwidth of the mmWave frequency attracts interest in radio frequency (RF) front‐end design which will be very much beneficial for security and cellular‐based applications such as intersatellite communication and automotive vehicle‐to‐vehicle communication. The RF front end requires low‐power and low‐noise receiver architecture for effective satellite communication, and it needs high throughput with maximum data transfer for cellular‐based applications. To address these challenges, this paper presents a novel low‐noise amplifier (LNA) operating from 57.12‐ to 66.25‐GHz frequency. The design is implemented using UMC 65‐nm CMOS process technology, and the post‐layout simulations are carried out using the Cadence Spectre RF tool. At 60 GHz, the LNA exhibits a power gain of 15.46 dB, minimum noise figure (NF) of 1.32 dB while consuming 6.59 mW from a 1.2‐V supply. The LNA employs the current reuse feedforward distortion cancelation technique to improve the third‐order input intercept point (IIP3) to +7.258 dBm. The proposed LNA provides a relatively better figure of merit compared to some of the recently proposed mmWave LNA architectures.

Review of Highly Mismatched III-V Heteroepitaxy Growth on (001) Silicon.

Si-based group III-V material enables a multitude of applications and functionalities of the novel optoelectronic integration chips (OEICs) owing to their excellent optoelectronic properties and compatibility with the mature Si CMOS process technology. To achieve high performance OEICs, the crystal quality of the group III-V epitaxial layer plays an extremely vital role. However, there are several challenges for high quality group III-V material growth on Si, such as a large lattice mismatch, highly thermal expansion coefficient difference, and huge dissimilarity between group III-V material and Si, which inevitably leads to the formation of high threading dislocation densities (TDDs) and anti-phase boundaries (APBs). In view of the above-mentioned growth problems, this review details the defects formation and defects suppression methods to grow III-V materials on Si substrate (such as GaAs and InP), so as to give readers a full understanding on the group III-V hetero-epitaxial growth on Si substrates. Based on the previous literature investigation, two main concepts (global growth and selective epitaxial growth (SEG)) were proposed. Besides, we highlight the advanced technologies, such as the miscut substrate, multi-type buffer layer, strain superlattice (SLs), and epitaxial lateral overgrowth (ELO), to decrease the TDDs and APBs. To achieve high performance OEICs, the growth strategy and development trend for group III-V material on Si platform were also emphasized.

Noise Immunity-Enhanced Capacitance Readout Circuit for Human Interaction Detection in Human Body Communication Systems

Recent healthcare systems based on human body communication (HBC) require human interaction sensors. Due to the conductive properties of the human body, capacitive sensors are most widely known and are applied to many electronic gadgets for communication. Capacitance fluctuations due to the fact of human interaction are typically converted to voltage levels using some analog circuits, and then analog-to-digital converters (ADCs) are used to convert analog voltages into digital codes for further processing. However, signals detected by human touch naturally contain large noise, and an active analog filter that consumes a lot of power is required. In addition, the inclusion of ADCs causes the system to use a large area and amount of power. The proposed structure adopts a digital-based moving average filter (MAF) that can effectively operate as a low-pass filter (LPF) instead of a large-area and high-power consumption analog filter. In addition, the proposed ∆C detection algorithm can distinguish between human interaction and object interaction. As a result, two individual digital signals of touch/release and movement can be generated, and the type and strength of the touch can be effectively expressed without the help of an ADC. The prototype chip of the proposed capacitive sensing circuit was fabricated with commercial 65 nm CMOS process technology, and its functionality was fully verified through testing and measurement. The prototype core occupies an active area of 0.0067 mm2, consumes 7.5 uW of power, and has a conversion time of 105 ms.

A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter

This article presents a fractional-N sampling type-I phase-locked loop (PLL). To overcome the impairments of a conventional type-I PLL, namely the frequency-tuning-dependent time offset and the narrow range of the sampling phase detector (SPD), which would prevent fractional-N synthesis, a novel digital phase error correction (DPEC) technique, operating in the background, is introduced, which provides robust low-jitter performance. Besides, a novel frequency locking method is presented, which provides fast lock and seamless hand-off to main PLL operation. The PLL has been fabricated in a 28-nm CMOS technology process, and it synthesizes frequencies from 11.9 to 14.1 GHz, achieving an rms jitter of 58.2 and 51.7 fs (integrated into the 1 kHz-100 MHz bandwidth) for a fractional-N and integer-N channel, respectively. The reference spur is as low as -73.5 dBc, while the worst case near-integer fractional spurs are lower than -63.2 dBc. With a power consumption of 18 mW, the jitter-power figure of merit is -252.1 dB (fractional-N) and -253.3 dB (integer-N). The locking time is below 9 μs for a 1-GHz frequency step. The synthesizer occupies 0.16 mm², including decoupling capacitors.