Abstract
Si-based group III-V material enables a multitude of applications and functionalities of the novel optoelectronic integration chips (OEICs) owing to their excellent optoelectronic properties and compatibility with the mature Si CMOS process technology. To achieve high performance OEICs, the crystal quality of the group III-V epitaxial layer plays an extremely vital role. However, there are several challenges for high quality group III-V material growth on Si, such as a large lattice mismatch, highly thermal expansion coefficient difference, and huge dissimilarity between group III-V material and Si, which inevitably leads to the formation of high threading dislocation densities (TDDs) and anti-phase boundaries (APBs). In view of the above-mentioned growth problems, this review details the defects formation and defects suppression methods to grow III-V materials on Si substrate (such as GaAs and InP), so as to give readers a full understanding on the group III-V hetero-epitaxial growth on Si substrates. Based on the previous literature investigation, two main concepts (global growth and selective epitaxial growth (SEG)) were proposed. Besides, we highlight the advanced technologies, such as the miscut substrate, multi-type buffer layer, strain superlattice (SLs), and epitaxial lateral overgrowth (ELO), to decrease the TDDs and APBs. To achieve high performance OEICs, the growth strategy and development trend for group III-V material on Si platform were also emphasized.
Highlights
As the big data is coming, continuing rapid development of Internet business, communication network moves toward the direction of high speed and large capacity
High-quality III-V heteroepitaxy on the Si substrate is crucial to the Si-based optoelectronic integration circuits (OEICs)
We reviewed the three major challenges of the Si based IIII-V heteroepitaxy: (1) anti-phase boundaries (APB); threading dislocation (TD); (3) stacking faults (SF)
Summary
As the big data is coming, continuing rapid development of Internet business, communication network moves toward the direction of high speed and large capacity. The defects management strategy was proposed to decrease the TDDs and APBs for group III-V material, improving the device performance Wafer bonding technologies, such as adhesive bonding [24,25], direct bonding [26], and fusion bonding [27,28], were adopted to form the advanced heterogeneous integration substrate platform. III-V layers on Si, fundamental challenges, such as the bandgap property of III-V semiconductors ma lattice mismatch, thermal mismatch, and substrate polarity difference, are the main limitaoptoelectronic devices compared theconstants indirect gap offorIV tions. Si. In III-V semiconductors, GaAs (4.1%) and InP (8.0%) have close lattice constants to IV grow III-V ontheSi.Ge,This mismatch can bring out on many relatively, especially whichhuge are more likely to realize the heteroepitaxy the Si defec substrate. At atomic steps of the substrate, (c) Stacking faults in the III-V material
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