An energy-efficient single-cycle RV32I microprocessor for edge computing applications

Abstract

With the advancement in the Internet of Things (IoT) and Wireless Sensor Node (WSN) applications computation on edge is preferred over computation on the cloud. However, due to limited resource availability in the edge environment, energy efficiency can be seen as the primary barrier in the growth of edge computing devices. In edge computing applications like wearable devices, forest monitoring systems, and other such applications, power is of utmost importance. The use of a complex, pipelined, general-purpose processor is redundant for such low-end applications and it leads to high power consumption. Hence, edge computing systems require low-power solutions while still maintaining a minimum performance level. In this work, an energy-efficient single-cycle RISC-V instruction set architecture (ISA) based RV32I processor is designed for low-end edge computing applications. The design incorporates base integer implementation of RISC-V ISA. The proposed computing system is designed using Verilog HDL and synthesized on Semi-conductor Laboratory (SCL) 180 nm CMOS process technology node. The synthesis tool reports power consumption of 14.7 mW at 50 MHz frequency with an area of 0.24 mm2. Though synthesis of this design reports area of 0.24 mm2, the design is taped out as a part of an available shuttle project where die size is fixed to 5 mm × 5 mm. The PNR (Place and Route) tool reports power consumption of 11.8 mW at an operating frequency of 40 MHz. A basic functional testing of proposed fabricated RV32I chip is carried out in laboratory experimental setup and results are presented. The comparison result shows that the proposed RV32I processor consumes 0.29 mW/MHz power which is less than state-of-the-art low-end processors. Hence, the proposed design is suitable for low-end edge computing applications.