CMOS Manufacturing Research Articles

(Invited) FinFET Technology

FinFET has been emerged as the leading device architecture for continuing CMOS scaling. It has entered mainstream CMOS manufacturing since 22nm node. In this paper, I will provide an overview on the challenges associated with CMOS scaling and articulate how FinFET circumvents those scaling challenges. Meanwhile, FinFET has its own unique issues related to device design and process integration. A detailed discussion on challenges and opportunities of FinFET will be discussed in detail. A general guidance for further scaling FinFET will be provided including channel materials, high-k/metal gate, strain techniques, device isolations. Advanced FinFET manufacturing techniques such as self-aligned multiple patterning and EUV lithography, selective epitaxy, and high-aspect ratio dielectric deposition will also be covered. Some common misconceptions about FinFET technology such as confusing technology node names adopted by different companies will be clarified. Finally, FinFET will be compared with other device architectures such as fully depleted SOI (FDSOI) and nanowire transistors. The advantages and drawbacks of each device architecture will be summarized.

(Invited) How to Integrate MEMS on Foundry-Fabricated CMOS Backplanes

Due to massive use of sensors and actuators in mobile and industrial applications smaller systems combined with low power consumption and higher versatility are required. As highly integrated and miniaturized devices System-on-chip (SoC) solutions are offering smallest feature sizes. Especially, MEMS-on-CMOS technology is often the choice to serve these demands. In order to reduce the development costs and time-to-market the combination of a standard CMOS processes from foundries with a subsequent MEMS processing is recommended. This technology offers a way to separate CMOS manufacturing and the specific developments of MEMS part. Fraunhofer IPMS employs bulk and surface micromachining for a large variety of MEMS devices e.g. spatial light modulators (SLM) and capacitive micro-machined ultrasonic transducers (CMUT). Based on a CMOS compatible inorganic sacrificial layer technique we will present essential requirements and challenges for the integration of surface micro-machined MEMS on foundry-fabricated CMOS backplanes.

Memcomputing (Memristor + Computing) in Intrinsic SiOx-Based Resistive Switching Memory: Arithmetic Operations for Logic Applications

In this paper, implication (IMP) operations are demonstrated in a circuit with two SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> -based memristors and a CMOS transistor. Specifically, a circuit with two one-diode and one-resistor (1D1R) memory elements and a transistor are designed to perform the IMP operations. A circuit consisting of a 4×4 crossbar 1D1R memristor array together with selection transistors is proposed and used to realize the functionality of a one-bit, full adder in 43 steps. Compared with CMOS logic circuits, the advantages and disadvantages of memristor-enabled logic circuits are discussed. This result suggests that the memristor-enabled logic circuit is most suitable for low-power and high-density applications, as well as a simple and robust approach to realize programmable memcomputing chips compatible with large-scale CMOS manufacturing technology.

Per-pixel energy calibration of photon counting detectors

Energy resolving performance of spectral CT systems is influenced by the accuracy of the detector's energy calibration. Global energy calibration maps a given threshold to the average energy response of all pixels of the detector. Variations arising from CMOS manufacturing processes and properties of the sensor cause different pixels to respond differently to photons of the same energy. Threshold dispersion adversely affects spectral imaging by degrading energy resolution, which contributes to blurring of the energy information. In this paper, we present a technique for per-pixel energy calibration of photon-counting x-ray detectors (PCXDs) that quantifies the energy response of individual pixels relative to the average response. This technique takes advantage of the measurements made by an equalized chip. It uses a known global energy map to quantify the effect of threshold dispersion on the energy response of the detector pixels across an energy range of interest. The proposed technique was assessed using a MARS scanner with an equalized Medipix3RX chip flip-bonded to 2 mm thick CdTe semiconductor crystal at a pitch of 110 μ m. Measurements were made of characteristic x-rays of a molybdenum foil. Results were compared between the case that the global calibration was used on its own and the case of using it in conjunction with our per-pixel calibration technique. The proposed technique quantified up to 1.87 keV error in energy response of 100 pixels of a selected region of interest (ROI). It made an improvement of 28.3% in average FWHM. The additional information provided by this per-pixel calibration technique can be used to improve spectral reconstruction.

An Efficient Bio-Chemical Sensor using Perpendicular Slot for Straight Resonator Integration in Health Care Application

Optical sensors are remarkable tools for analyze detection in biochemical, health and environmental applications. The use of photons for sensing makes possible multi-dimension (intensity, wavelength, phase, and polarization) and remote interrogation, immunity to electromagnetic interferences, multiplexed detection, and availability of well-established technologies from communication industries: e.g. lasers of almost any wavelength, detector arrays, micro-/nano-machining, waveguides, and high speed links. In addition, optical frequencies coincide with a wide rage of physical properties of bio-related materials in nature. A minimized and incorporated mark free refractometric bio- chemical sensor in view of silicon-on- insulator (SOI) is proposed and completely learned at the media transmission wavelength of ? = 1550 ????. This gadget fused a three dimensional (3D) Fabry-Perot depressions in the nano-scale administration with greatest impression range around 470 × 473 ????2. A reverberation move (??????????) of 5.2 ???? is accounted for an ultra-thin (5 ????) bio-layer detecting. In addition, an enhanced greatest affectability (?? = 820 ????/??????) is likewise accomplished for mass refractive file change in environment. As a chemical sensor, low identification restrict (???? = ??.?? × ????-????????) likewise can be conceivable to accomplish by this gadget. All the numerical examinations and advancements were done in frequency area by a numerically proficient and thorough full vectorial h-field based two dimensional (2D) and three dimensional (3D) finite component strategies (FCS). A 3D-FCS code is produced and used to discover the wavelength conditions of the resonator. Conceivable outcomes of simple CMOS manufacture and reconciliation openings make this structure as an imminent and proficient lab-on-chip gadget.

Titanium Silicide on Si:P With Precontact Amorphization Implantation Treatment: Contact Resistivity Approaching $1 \times 10^{-9}$ Ohm-cm2

In recent CMOS technology, extreme shrinking of contact area at source/drain regions raises serious concerns of high metal/semiconductor contact resistance. Confronting this problem, we introduce a precontact amorphization implantation plus Ti silicidation technique (PCAI + TiSi x ) and achieve ultralow contact resistivity ( $\rho _{c}$ ) of (1.3 – 1.5) $\times 10^{-9} ~\Omega \cdot \text {cm}^{2}$ on Si:P. This PCAI + TiSi x technique utilizes light amorphization (low-energy implantation), thin Ti and TiSi x film, and moderate thermal budget (500 °C –550 °C): these features are compatible with modern CMOS manufacturing. Moreover, the PCAI + TiSi x -induced $\rho _{c}$ reduction is proved universal on both n- and p-Si. With additional characterizations, we find that the silicidation-induced $\rho _{c}$ variation is not merely a Schottky barrier height tuning effect. The electrical and physical characterizations suggest that the low $\rho _{c}$ is strongly correlated with the formation of interfacial TiSi x crystallites between amorphous TiSi alloy and Si.

Device to circuit reliability correlations for metal gate/high-k transistors in scaled CMOS technologies

Metal gate/high-k stacks are in CMOS manufacturing since the 45nm technology node. To meet technology performance and yield targets, gate stack reliability is constantly being challenged. Assessing the associated reliability risk for CMOS products relies on a solid understanding of device to circuit reliability correlations. In this paper we summarize our findings on the correlation between device reliability and circuit degradation and highlight areas for future work to focus on.

Comparative Analysis of Growth Rate Enhancement and Ge Redistribution during Silicon-Germanium Oxidation by Rapid Thermal Oxidation

The demand for higher speed and lower power consumption ICs has motivated research for higher mobility channel materials (1). Compressively strained SiGe is known to feature higher hole mobility than Si and is largely compatible with the Si CMOS manufacturing platform. Besides, the FDSOI transistor architecture allows power consumption reduction (2), thus making SiGe-On-Insulator (SGOI) channels promising. SGOI layers can be fabricated by the so-called condensation technique, which is based on concurrent Si selective thermal oxidation of SiGe and SiGe composition homogenization by Si and Ge interdiffusion (see Figure 1) (3). Therefore, a sound understanding of kinetics of oxidation and interdiffusion of SiGe is required to develop optimized SGOI structures. SiGe dry oxidation rate has been reported to be higher (4) than or equal (5)(6) to the one of Si. It therefore remains unclear. Few groups investigated Rapid Thermal Oxidation (RTO) (4) while most of them looked at furnace oxidation. Moreover, most studies only considered the initial Ge content to compare oxidation kinetics. Indeed, the Ge concentration below the SiGe-oxide interface is strongly varying with time because of two mechanisms: firstly, the Si-selective oxidation of SiGe tends to pile-up Ge below the oxidizing interface; and secondly, interdiffusion of SiGe favors homogenization of the layer (6). This paper focuses on the oxidation rate of SiGe in regards to the varying Ge concentration in the SiGe layer for various oxidation conditions. Thick (> 20 nm) SiGe layers with either 10% or 30% Ge concentrations were epitaxially grown on bulk Si wafers. Oxidation was performed by RTO in 1 atmosphere of pure O2, with different oxidation temperatures and durations. Oxide thickness and SiGe composition versus depth were measured by Spectroscopic Ellipsometry and X-Ray Reflectivity, and by Secondary Ion Mass Spectroscopy respectively. Figure 2 shows the Ge concentration profile below the oxide. A rapid creation of a pile-up layer is observed at all temperatures. Then, three regimes of evolution of the pile-up layer are distinguished: the Ge concentration at the oxidizing interface (a) increases, (b) is constant, and (c) decreases. The regime of evolution of the pile-up layer is determined by a competition between the oxidation speed and the interdiffusion speed. As schematically illustrated Figure 3, the interdiffusion speed overcomes the oxidation one at higher temperatures because the activation energy of interdiffusion in SiGe ([4,5] eV (7)) is well above the one of SiGe oxidation ([2,2.6] eV (4)). Phrased in a different way, the temperature dependence of interdiffusion is higher than the oxidation one. Figure 4 shows the oxide thickness versus the oxidation duration for dry RTO at 900°C, 1000°C and 1100°C. A higher oxidation rate is observed for SiGe compared to Si for all temperatures. Then, to highlight the effect of the Ge concentration at the oxidizing interface, we fitted the curves to extract oxidation rates for each oxidation conditions. We define the Growth Rate Enhancement (GRE) as the ratio of the oxidation rate of SiGe to the one of Si at a given oxide thickness and for identical oxidation conditions. It is indeed important to highlight that comparing oxidation rates at the same oxide thickness is mandatory: if we want to examine the effect of Ge on the oxidation rate, we have to take into consideration the fact that the oxidation rate also decreases with the oxide thickness. Such an approach allows us to freeze the system and to find more easily correlations. We report on Figure 5 four GRE values extracted from our data versus the Ge concentration at the oxidizing interface. We thus observe that the higher the Ge concentration at the oxidizing interface is, the higher the GRE tends to be. We thus showed that Ge redistribution by interdiffusion during SiGe oxidation can follow different regimes. We also evidenced that for dry RTO conditions, the higher the Ge concentration at the oxidizing interface is, the higher the GRE is. Understanding the interdependence of these two mechanisms is essential to get an accurate picture of the condensation process. Therefore, data for dry RTO will be completed and an in-depth discussion will be led. A similar study will also be conducted for a wet oxidation process called In-Situ Steam Generation (ISSG). (1) Pillarisetty, R., Nature 479.7373 (2011): 324-328. (2) Weber, O., et al., VLSIT IEEE, 2014. (3) Tezuka, T., et al., JJAP 40.4S (2001): 2866. (4) Spadafora, M., et al. MSSP 8.1 (2005): 219-224. (5) LeGoues, et al., APL 54.7 (1989): 644-646. (6) Long, E., et al., PSS (a) 209.10 (2012): 1934-1939. (7) Kube, R., et al., JAP 107.7 (2010): 073520. Figure 1

(Invited) Memcomputing (Memristor + Computing) in Intrinsic SiOx-Based Resistive Switching Memory

This study focuses on memcomputing (Memristor + Computing) in intrinsic SiOx-based resistive switching memory. Specifically, we investigate neuromorphic computing by a device with biological synaptic behaviors in integrating silicon oxide (SiOx) resistive switching memory with Si diodes. Minimal synaptic power consumption due to sneak-path current has been achieved and the capability for spike-induced synaptic behaviors has been demonstrated, representing critical milestones for the application of SiO2–based materials in future neuromorphic computing. The detailed biological synaptic behaviors such as long-term potentiation (LTP), long-term depression (LTD) and spike-timing dependent plasticity (STDP) are demonstrated systematically using a comprehensive analysis of spike-induced waveforms. We will also discuss a implementation technique of implication operations by using SiOx-based memristors in TaN/SiOx/Si. The implication function and its truth table have been implemented. The key factors for the operation of material implication, such as load resistance, characteristics of the memristor, and design tradeoffs have been investigated. Furthermore, we have demonstrated implication operation using a circuit with two SiOx-based memristor and CMOS transistor. A circuit with two one-diode and one resistor (1D-1R) memory elements and a transistor are designed to perform implication operations. A circuit consisting of a 4 × 4 crossbar structure 1D1R memristor array together with the select transistors is proposed. Based on this circuit, a total of 48 steps of operations are performed to realize the functionality of a one bit full adder. The advantages and disadvantages of the memristor enabled logic circuit are compared with CMOS logic circuits. The experimental results suggest a simple, robust approach to realize programmable memcomputing chips compatible with large-scale CMOS manufacturing technology. (* This paper is invited by ECS 2016 Honolulu Meeting.)

(Invited) Chalcogenide Glasses for Planar Devices

Semiconducting chalcogenide glasses (ChGs) are well known for their amenability to film fabrication and intriguing optical properties, namely transparency in key mid-infrared wavelength regimes where target analytes have fundamental molecular fingerprints. To realize next generation photonic sensing devices, high production and low cost is sought by leveraging the existing capabilities and knowledge-base of microelectronics, such as through the compositional design of materials that are compatible with CMOS manufacturing techniques. Subsequent improvements in overall device performance through reduced optical loss, and increased accuracy, sensitivity, and specificity enables these sensors to rival the capabilities of larger and costlier sensing technologies such as Fourier transform infrared (FTIR) spectroscopy. Thus, ChGs are poised to play a leading role in miniaturized chemical sensing technology, which is enabled through various techniques of film deposition on Si substrates and post-processing to precisely fabricate micron-scale structures and components. Amongst these techniques, this presentation highlights recently developed 2-D and 3-D printing of ChG films from solution by electrospray, a process which is compatible with continuous manufacturing, engineered non-uniform thickness films, and direct writing of coatings with compositional gradients. In addition, this work has also advanced the controlled crystallization of both bulk and film forms of ChG by laser exposure and heat treatment, which allows further tunability of the material properties and an additional strategy to obtaining spatial gradients in material properties. This presentation will discuss the development of the ChG materials processing “toolbox” in light of the oncoming maturation of microphotonic chemical sensors.

Demonstration of Synaptic Behaviors and Resistive Switching Characterizations by Proton Exchange Reactions in Silicon Oxide.

We realize a device with biological synaptic behaviors by integrating silicon oxide (SiOx) resistive switching memory with Si diodes. Minimal synaptic power consumption due to sneak-path current is achieved and the capability for spike-induced synaptic behaviors is demonstrated, representing critical milestones for the use of SiO2–based materials in future neuromorphic computing applications. Biological synaptic behaviors such as long-term potentiation (LTP), long-term depression (LTD) and spike-timing dependent plasticity (STDP) are demonstrated systematically using a comprehensive analysis of spike-induced waveforms, and represent interesting potential applications for SiOx-based resistive switching materials. The resistive switching SET transition is modeled as hydrogen (proton) release from (SiH)2 to generate the hydrogen bridge defect, and the RESET transition is modeled as an electrochemical reaction (proton capture) that re-forms (SiH)2. The experimental results suggest a simple, robust approach to realize programmable neuromorphic chips compatible with large-scale CMOS manufacturing technology.

(Invited) Thin Film Technologies for Micro/Nano Systems; A Review

Thin film technology is employed since ages in the field of art, household appliances, optics, metallurgy etc. But the invention of solid state electronic devices, more specifically integrated circuits, really boosted thin film technology to a level of atomic precision in a high volume manufacturing environment. Today the mass production of nano electronic devices principally relies on the deposition and patterning on thin films. Consequently the performance of these devices and systems is determined by the relevant properties of patterned thin films.For conventional applications in the microelectronic domain, the function of a thin film is either an insulator or a conductor; the electrical properties of such films are of overriding importance in the application. And because silicon is the preferred substrate material for current and future CMOS technologies, the thin film deposition technologies must be silicon compatible. However, the continuous scaling of CMOS brings conventional thin films beyond physical limitations. Therefore novel materials like high K gate dielectrics and low K intermetallic dielectrics where introduced in the CMOS process flow. Moreover in combination with the electrical parameters also other domains like mechanical stress needs to be controlled to enhance the charge carrier mobility, often complicating the formation of the film stack and subsequent processing. In addition the increasing aspect ratio of downscaled and novel device structures like fin-fet also put constraints on the deposition techniques. Consequently, over time a broad portfolio of thin film deposition technologies and thin films properties has been developed.But the application of thin films is not limited to IC technology only, also the fabrication microelectronic mechanical systems (MEMS), biomedical devices, solid state lighting technology, and novel approaches to micro and nano system integration, all rely (partly) on thin film technologies. This class of non-CMOS technologies will be further referred to as micro/nano systems technology. The device scaling in micro/nano system technology follows different rules compared with CMOS and spans multi domains and multi scales, even more than in CMOS.The broad portfolio of thin film technologies originally developed for CMOS now employed in micro/nano system technology today churns out a large number of different process sequences to yield a broad spectrum of device structures process flows. Novel discoveries in the domain of nano science, biology, the technology push in solid state lighting and the further industrialisation of MEMS and NEMS will broaden this technology portfolio even more. And contrary to a CMOS transistor, the structure and manufacturing process of micro/nano devices is strongly dictated by its application. Hence a micro/nano system does not have a generic structure, and in some cases very specific thin films and corresponding deposition technologies are required.CMOS scaling as we know may end in the not too distant future, while the exploration of micro and specifically nano systems rise from the ranks. Novel 3D devices, heterogeneous integration schemes and micro/nano system will emerge to provide increasing functionality. The expanding application domain of newly developed micro/nano systems will result in new thin film deposition technologies, tools and new requirements. In addition, the diversity in device structures, the multi scale and multi domain applications are a challenging task for the numerical simulation of such systems.In this paper, the major applications of thin film technologies, applied in micro/nano system technology today will be reviewed, the diversity will be addressed and novel structures will be discussed with an outlook into the future.

Radiation Effects in SiGe Technology

Silicon-Germanium (SiGe) technology effectively merges the desirable attributes of conventional silicon-based CMOS manufacturing (high integration levels, at high yield and low cost) with the extreme levels of transistor performance attainable in classical III-V heterojunction bipolar transistors (HBTs). SiGe technology joins together on-die high-speed bandgap-engineered SiGe HBTs with conventional Si CMOS to form SiGe BiCMOS technology, including all the requisite RF passive elements and multi-level thick-Al metalization required for high-speed circuit design. Such an silicon-based integrated circuit technology platform presents designers with an ideal division of labor for realizing optimal solutions to many performance-constrained mixed-signal (analog + digital + RF) systems. The unique bandgap-engineered features of SiGe HBTs enable several key merits with respect to operation across a wide variety of so-called “extreme environments”, potentially with little or no process modification, ultimately providing compelling advantages at the circuit and system level, across a wide class of envisioned commercial and defense applications. Here we give an overview of this interesting field, focusing primarily on the intersection of SiGe HBTs, and circuits built from them, with radiation-intense environments such as space.

High Temperature Digital and Analogue Integrated Circuits in Silicon Carbide

Silicon Carbide devices are capable of operating as a semiconductor at high temperatures and this capability is being exploited today in discrete power components, bringing system advantages such as reduced cooling requirements [1]. Therefore there is an emerging need for control ICs mounted on the same modules and being capable of operating at the same temperatures. In addition, several application areas are pushing electronics to higher temperatures, particularly sensors and interface devices required for aero engines and in deep hydrocarbon and geothermal drilling. This paper discusses a developing CMOS manufacturing process using a 4H SiC substrate, which has been used to fabricate a range of simple logic and analogue circuits and is intended for power control and mixed signal sensor interface applications [2]. Test circuits have been found to operate at up to 400°C. The introduction of a floating capacitor structure to the process allows the use of switched capacitor techniques in mixed signal circuits operating over an extended temperature range.

The status and trend of novel process and technology in nano-IC manufacturing

The technology development of micro-nano electronics in global IC industry is summarized and reviewed in the present paper. There are many challenges and opportunities as the innovative devices and materials have gradually been applied to IC manufacture. As ITRS 2011 Roadmap shows that gate length will shrink to 20 nm in 2013, the industry mainstream manufacturing technologies of the nano-electronics seems moving toward the goal. It is well known that the IC technology development basically depends on material science. In Section 2, some new material and process technologies are highlighted, such as strained silicon, high K and metal gate, ultra-low K, 450 mm silicon wafer, and immersion lithography technologies are the foundation of IC manufacture. The process integration for advanced CMOS manufacture technology is discussed in Section 3. As an example, 20 nm process flow scheme is explained and some comparison is made to the precious generation technology. The main process flow difference between 28 nm technology and 20 nm technology is illustrated and some explanations are presented. In Section 4, 3D system packaging technology is introduced. Some preliminary TSV experimental data made by SMIC are shown. It is expected that 3D TSV Wide I/O would eventually be inevitable in 28 nm production and beyond. In Section 5, the research and development of nonvolatile memory are summarized, such as RRAM, PcRAM and MRAM. Some lab experimental and measurement results from SMIC are demonstrated. It is believed that PcRAM, which is relatively mature technology, mass production will probably come up in the mainland in a few years. In Section 6, a couple of new transistor architectures are introduced and some experimental data are demonstrated, such as local SOI and GAA, and some experimental data are shown. Finally, the comments for domestic R&D strategy in IC area are proposed to future IC R&D direction.

Experimental Validation of the Drain Current Analytical Model of the Fully Depleted Diamond SOI nMOSFETs by Using Paired T-test Statistical Evaluation

The focus of this work is to validate the drain current analytical model of the Fully Depleted Diamond SOI nMOSFETs, by applying the paired t-test statistical evaluation with experimental data of the six different samples of integrated circuits containing different Diamond SOI MOSFETs and Conventional ones counterparts. Two parameters are considered in this work: maximum transconductance and saturation drain current. We observe that, for the most cases (worst case is around 85% of the repeatability for the saturation drain current), the Diamond drain current analytical model is capable to reproduce a similar statistical behavior than the one observed for the conventional SOI nMOSFET counterpart, considering the same bias conditions and SOI CMOS manufacturing process of the integrated circuits.

Evaluation of direct patternable inorganic spin-on hard mask materials using electron beam lithography

Two inorganic non-chemically amplified resists (XE15CB and XE15IB) were investigated. The resists are based on hafnium oxide sulfate and spin-cast from aqueous solution. They differ in sensitivity and resolution. In contrast to other studies, the materials were coated for the first time on 300 mm wafers and exposed on a 50 kV VISTEC SB3050DW variable shaped electron beam direct writer in a near-production environment at Fraunhofer CNT. In this paper, the evaluation of this resist family and its feasibility for production will be discussed. The resists were evaluated in terms of contrast, sensitivity and resolution. The process characteristics required for CMOS manufacturing such as delay stability were also examined. Furthermore, by exposing a large SRAM pattern (design CD of 22 nm), the exposure of a real application pattern was demonstrated.

A Light-Field Image Sensor in 180 nm CMOS

This paper presents a CMOS image sensor which captures local incident angle and intensity information from the light it records. The 400×384 pixel array employs 7.5 μm angle-sensitive pixels, which use pairs of local diffraction gratings above a photodiode to detect incident angle. The gratings are implemented with the metal interconnect layers of CMOS manufacturing technology and therefore require no post-processing or external optics. Fabricated in a 180 nm mixed-mode CMOS process, the sensor requires only a single lens to create a light-field image. Using the information contained in a single image, we demonstrate range finding with 2.5 mm precision at 1 m and post-capture refocus on complex visual scenes.

The status and trend of novel process and technology in nano-IC manufacturing

The technology development of micro-nano electronics in global IC industry is summarized and reviewed in the present paper. There are many challenges and opportunities as the innovative devices and materials have gradually been applied to IC manufacture. As ITRS 2011 Roadmap shows that gate length will shrink to 20 nm in 2013, the industry mainstream manufacturing technologies of the nano-electronics seems moving toward the goal. It is well known that the IC technology development basically depends on material science. In Section 2, some new material and process technologies are highlighted, such as strained silicon, high K and metal gate, ultra-low K, 450 mm silicon wafer, and immersion lithography technologies are the foundation of IC manufacture. The process integration for advanced CMOS manufacture technology is discussed in Section 3. As an example, 20 nm process flow scheme is explained and some comparison is made to the precious generation technology. The main process flow difference between 28 nm technology and 20 nm technology is illustrated and some explanations are presented. In Section 4, 3D system packaging technology is introduced. Some preliminary TSV experimental data made by SMIC are shown. It is expected that 3D TSV Wide I/O would eventually be inevitable in 28 nm production and beyond. In Section 5, the research and development of nonvolatile memory are summarized, such as RRAM, PcRAM and MRAM. Some lab experimental and measurement results from SMIC are demonstrated. It is believed that PcRAM, which is relatively mature technology, mass production will probably come up in the mainland in a few years. In Section 6, a couple of new transistor architectures are introduced and some experimental data are demonstrated, such as local SOI and GAA, and some experimental data are shown. Finally, the comments for domestic R&D strategy in IC area are proposed to future IC R&D direction.

Ge quantum dot arrays grown by ultrahigh vacuum molecular-beam epitaxy on the Si(001) surface: nucleation, morphology, and CMOS compatibility

Issues of morphology, nucleation, and growth of Ge cluster arrays deposited by ultrahigh vacuum molecular beam epitaxy on the Si(001) surface are considered. Difference in nucleation of quantum dots during Ge deposition at low (≲600°C) and high (≳600°C) temperatures is studied by high resolution scanning tunneling microscopy. The atomic models of growth of both species of Ge huts--pyramids and wedges-- are proposed. The growth cycle of Ge QD arrays at low temperatures is explored. A problem of lowering of the array formation temperature is discussed with the focus on CMOS compatibility of the entire process; a special attention is paid upon approaches to reduction of treatment temperature during the Si(001) surface pre-growth cleaning, which is at once a key and the highest-temperature phase of the Ge/Si(001) quantum dot dense array formation process. The temperature of the Si clean surface preparation, the final high-temperature step of which is, as a rule, carried out directly in the MBE chamber just before the structure deposition, determines the compatibility of formation process of Ge-QD-array based devices with the CMOS manufacturing cycle. Silicon surface hydrogenation at the final stage of its wet chemical etching during the preliminary cleaning is proposed as a possible way of efficient reduction of the Si wafer pre-growth annealing temperature.