Abstract
Metal gate/high-k stacks are in CMOS manufacturing since the 45nm technology node. To meet technology performance and yield targets, gate stack reliability is constantly being challenged. Assessing the associated reliability risk for CMOS products relies on a solid understanding of device to circuit reliability correlations. In this paper we summarize our findings on the correlation between device reliability and circuit degradation and highlight areas for future work to focus on.
Full Text
Published Version
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call