CMOS Manufacturing Research Articles

Statistical optimization and manufacturing sensitivity analysis of 0.18 μm SOI MOSFETs

A comprehensive approach based on TCAD and statistical methods has been demonstrated for deep submicron SOI CMOS process optimization and manufacturing sensitivity analysis. Second-order response surface models were fitted to ten device characteristics based on 15 processing conditions identified as significantly affecting the CMOS process. The optimized 0.18 μm SOI CMOS process, representative of deep submicron SOI technology currently under consideration by industry, was determined by numerical analysis of the generated models. A two part sensitivity analysis was then conducted for the optimized process. A Monte Carlo analysis technique was applied to a set of reduced response models to determine the sensitivity of the device characteristics to some anticipated manufacturing process random variations. Results for a 0.18 μm PD SOI CMOS technology are presented, providing optimized process conditions meeting desired device performance measures, and indicating no conspicuous device performance degradation by anticipated manufacturing process variations.

Novel Device Concept for Voltage-Bias Controlled Color Detection in Amorphous Silicon Sensitized Cmos Cameras

ABSTRACTWe present a novel sensor concept comprising a new contacting scheme for voltage-bias con- trolled thin film photodiode arrays on CMOS readout chips. Our unilateral contact structure greatly facilitates manufacturing of the sensor system. Moreover, the novel contacting scheme most efficiently suppresses crosstalk between neighboring pixels. The respective devices are ready for operation and testing directly after deposition of the amorphous silicon based sensor layers. No extra transparent front contact is needed, no patterning and no connection between the topmost layer of the thin film stack and the underlying readout chip. Due to the lack of a metal oxide front contact, contamination of CMOS manufacturing equipment with tin, zinc or similar materials is definitely avoided. Thus, for the first time, a sensor concept with complete CMOS process compatibility is demonstrated. Our new sensor structure allows for a considerable reduction in manufacturing cost of high performance optical detection systems. As a proof of concept, we present detailed investiga- tions on current-voltage characteristics, dynamic behavior and spectral response of 0.1-inch test structures. Down-scaling to pixel sizes in the micron range is evaluated by semi-empirical numerical modeling and proves easily feasible.

Defect-oriented testability for asynchronous ICs

For a CMOS manufacturing process, asynchronous ICs are similar to synchronous ICs. The defect density distributions are similar, and hence, so are the fault models and fault-detection methods. So, what makes us think that asynchronous circuits are much harder to test than synchronous circuits? Because the effectiveness of best known test methods for synchronous circuits drops when applied to asynchronous circuits? They may very well be a temporal hurdle. Many test methods have already been reevaluated and successfully adapted from the synchronous to the asynchronous test domain. The paper addresses one of the final hurdles: I/sub DDQ/ testing. This type of test method, based on measuring the quiescent power supply current, is very effective for detecting (resistive) bridging faults in CMOS circuits. Detection of bridging faults is crucial, because they model the majority of today's manufacturing defects. I/sub DDQ/ fault effects are sensitized in a particular state or set of states and can only be detected if we stop the circuit operation right there. This is a problem for asynchronous circuits, because their operation is self-timed. In the paper, we quantify the impact of self timing on the effectiveness of I/sub DDQ/-based test methods for bridging faults, and propose a Design-for-Test (DfT) approach to develop a low-cost DfT solution. For comparison, we do the same for logic voltage testing and stuck-at faults. The approach is illustrated on circuits from Tangram, the asynchronous design-style employed at Philips Research, but it is applicable to asynchronous circuits in general.

Selective Rapid Thermal Chemical Vapor Deposition of Titanium Disilicide on Silicon and Polysilicon

ABSTRACTSelective rapid thermal chemical vapor deposition (RTCVD) of TiSi2 is a promising alternative to the conventional self-aligned suicide (SALICIDE) process to form low-resistivity contacts to ultra-shallow source/drain junctions of deep submicron MOS transistors. The process makes use of TiCl4 and SiH4 as the Ti and Si source gases in a temperature range of 750 – 825 °C. The primary advantage of the process over the conventional SALICIDE process is that by providing sufficient levels of Si from the gas phase, junction consumption can be eliminated. Furthermore, the process eliminates wet etch and reduces the number of process steps from four to one. For the process to be compatible with CMOS manufacturing, low-resistivity TiSi2 deposition must be achieved on both source/drain junctions as well as the poly cry stalline silicon gate electrode. It is the objective of this paper to compare basic characteristics of the process on these two surfaces. The results indicate that the crystallinity of the surface on which TiSi2 is deposited can impact the nature of the deposited film. Our experimental results indicate enhanced Si consumption on polysilicon, smaller TiSi2 grains and consequently higher sheet resistance. However, the process conditions and TiSi2 thickness can be optimized to achieve consumption free TiSi2 deposition on the junctions with acceptable performance on polysilicon.

Integrated cost and productivity learning in CMOS semiconductor manufacturing

This paper describes a cost and productivity learning process that was carried out on a large-capacity CMOS manufacturing line at the IBM Burlington facility from 1991 to 1993. Major productivity gains were realized through process and tool improvements affecting yield, and through work-in-progress optimization and scrap reduction. Significant cost learning was also accomplished through tool cost management, capital depreciation and space cost reductions, and manpower optimization.

Establishment of a Radiation Hardened CMOS Manufacturing Process

A radiation hardened metal gate CMOS IC process, tolerant to doses in excess of 106 rads (Si), has been established by making necessary modifications to a standard process. These modifications are described, a definition of circuit radiation hardness is discussed, and typical electrical performance characteristics as a function of radiation dose are presented. Procedures are described for assuring the hardness of finished product. Operating life test data indicates that the process is inherently reliable.