CMOS Manufacturing Research Articles

A DfT Strategy for Guaranteeing ReRAM’s Quality after Manufacturing

Memristive devices have become promising candidates to complement the CMOS technology, due to their CMOS manufacturing process compatibility, zero standby power consumption, high scalability, as well as their capability to implement high-density memories and new computing paradigms. Despite these advantages, memristive devices are susceptible to manufacturing defects that may cause faulty behaviors not observed in CMOS technology, significantly increasing the challenge of testing these novel devices after manufacturing. This work proposes an optimized Design-for-Testability (DfT) strategy based on the introduction of a DfT circuitry that measures the current consumption of Resistive Random Access Memory (ReRAM) cells to detect not only traditional but also unique faults. The new DfT circuitry was validated using a case study composed of a 3x3 word-based ReRAM with peripheral circuitry implemented based on a 130 nm Predictive Technology Model (PTM) library. The obtained results demonstrate the fault detection capability of the proposed strategy with respect to traditional and unique faults. In addition, this paper evaluates the impact related to the DfT circuitry’s introduced overheads as well as the impact of process variation on the resolution of the proposed DfT circuitry.

Enhancing ferroelectric performance in hafnia-based MFIS capacitor through interface passivation and bulk doping

In recent times, there has been a notable surge of interests in hafnia (HfO2)-based ferroelectrics, primarily due to their remarkable ferroelectric properties employed in ultra-thin configurations, alongside their compatibility with the conventional CMOS manufacturing process. In order to harness the full potential of HfO2-based films for high-performance non-volatile memory applications, it is imperative to enhance their ferroelectric characteristics and durability. This study introduces a straightforward approach aimed at augmenting the ferroelectric performance of Hf x Zr1−x O2 (HZO) films deposited on silicon (Si) substrates through the engineering of oxygen vacancies (V O). The results of this endeavor demonstrate a significant enhancement in ferroelectric performance, characterized by a 2Pr value of 47 μC cm−2 and impressive endurance, enduring up to 108 cycles under an 8 MV cm−1 electric field without the need of a wake-up process. This marked improvement can be attributed to a dual-pronged approach, involving the incorporation of an Al2O3 interlayer and the introduction of Al atoms into the HZO film. The Al2O3 interlayer primarily serves to mitigate the presence of oxygen vacancies at the interface, while the introduction of Al dopants elevates the concentration of oxygen vacancies within the bulk material. This modulation of oxygen vacancy concentration proves instrumental in facilitating the formation of a ferroelectric o-III phase within the HZO-based films, thereby further augmenting their ferroelectric performance. This innovative and effective strategy offers an alternative avenue for enhancing the ferroelectric properties of materials characterized by a fluorite crystal structure.

Extreme ultraviolet lithography reaches 5 nm resolution.

Extreme ultraviolet (EUV) lithography is the leading lithography technique in CMOS mass production, moving towards the sub-10 nm half-pitch (HP) regime with the ongoing development of the next generation high numerical aperture (high NA) EUV scanners. Hitherto, EUV interference lithography (EUV-IL) utilizing transmission gratings has been a powerful patterning tool for the early development of EUV resists and related processes, playing a key role in exploring and pushing the boundaries of photon-based lithography. However, achieving patterning with HPs well below 10 nm using this method presents significant challenges. In response, this study introduces a novel EUV-IL setup that employs mirror-based technology and circumvents the limitations of diffraction efficiency towards the diffraction limit that is inherent in conventional grating-based approaches. The results are line/space patterning of the HSQ resist down to HP 5 nm using the standard EUV wavelength 13.5 nm, and the compatibility of the tool with shorter wavelengths beyond EUV. Mirror-based interference lithography paves the way towards the ultimate photon-based resolution at EUV wavelengths and beyond. This advancement is vital for scientific and industrial research, addressing the increasingly challenging needs of nanoscience and technology and future technology nodes of CMOS manufacturing in the few-nanometer HP regime.

Incomplete charge transfer in CMOS image sensor caused by Si/SiO2 interface states in the TG channel

CMOS image sensors produced by the existing CMOS manufacturing process usually have difficulty achieving complete charge transfer owing to the introduction of potential barriers or Si/SiO2 interface state traps in the charge transfer path, which reduces the charge transfer efficiency and image quality. Until now, scholars have only considered mechanisms that limit charge transfer from the perspectives of potential barriers and spill back effect under high illumination condition. However, the existing models have thus far ignored the charge transfer limitation due to Si/SiO2 interface state traps in the transfer gate channel, particularly under low illumination. Therefore, this paper proposes, for the first time, an analytical model for quantifying the incomplete charge transfer caused by Si/SiO2 interface state traps in the transfer gate channel under low illumination. This model can predict the variation rules of the number of untransferred charges and charge transfer efficiency when the trap energy level follows Gaussian distribution, exponential distribution and measured distribution. The model was verified with technology computer-aided design simulations, and the results showed that the simulation results exhibit the consistency with the proposed model.

High-Performance Monolithic Integration of III-V QD Lasers on Si Substrates

With the development of digital processes, the speed and efficiency of information exchange has increased to a great extent. Silicon-based photonics allows for large-scale photonic integration through CMOS manufacturing processes, the advantages of which lie in the low cost, low energy consumption and high quality of such processes. Currently, silicon-based monolithic integrated quantum dot lasers have achieved lifetimes comparable to those of heterogeneous integrated lasers and are even available for commercial applications. The silicon photonic platform also offers low-loss passive devices, as well as high-speed optical modulators and photodetectors. However, device performance suffers due to differences in physical properties between group III-V lasers and substrate materials, an important factor limiting the development of silicon-based monolithic integrated quantum dot lasers. This paper reviews the respective characteristics of silicon-based monolithic and heterogeneous integration. The advantages of monolithically integrated III-V quantum dot lasers over heterogeneous integration are highlighted, as well as the challenges, solutions and recent developments.

45‐4: MicroLED Display Life Cycle Assessment

This paper addresses the life cycle assessment of a MicroLED display component: 3D integration of CMOS and active GaN on silicon LED module. Along different life cycle phases of this technology, results explicit the impacts of the CMOS manufacturing flow on one hand and the epitaxy step on the other hand.

Heterogeneous Integration of III-V Lasers in a 300 mm CMOS Manufacturing Line

AIM Photonics has developed a high precision laser attach process using an ultra-precise ASM Amicra NANO 300 mm die-to-wafer flip-chip bonder and integrated solder stamping system. Laser die are placed with high accuracy (<1 µm) and soldered to form a AuSn eutectic bond. This photonic platform has low optical losses, with SiN waveguides measuring on the order of 0.4 dB/cm and a calculated laser-to-waveguide coupling loss of 1.86 dB.

Highly Reliable and Secure PUF Using Resistive Memory Integrated Into a 28 nm CMOS Process

Owing to the increased demand for secure communication channels and authentication steps, physical unclonable functions (PUFs) are increasingly important for hardware security. In this article, we report a novel PUF architecture and generation scheme that utilizes the inherent program-time variation of resistive random access memory (ReRAM) cells as an entropy source. ReRAM cells are integrated into a standard 28 nm CMOS manufacturing process, and also show robust non-volatile memory operation. We generated a PUF data set larger than 10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\text{8}}$</tex-math> </inline-formula> bits and verified its randomness using a standard NIST test suite. Further verifications such as inter-and intra-hamming distance, 150 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> C data retention of PUF bits, and spatial co-relation tests confirm the high reliability of the generated PUF keys.

Reconfigurable Split Ring Resonators by MEMS-Driven Geometrical Tuning.

A novel approach for dynamic microwave modulation is proposed in the form of reconfigurable resonant circuits. This result is obtained through the monolithic integration of double split ring resonators (DSRRs) with microelectromechanical actuators (MEMS) for geometrical tuning. Two configurations were analyzed to achieve a controlled deformation of the DSRRs' metamaterial geometry by mutual rotation or extrusion along the azimuthal direction of the two constituent rings. Then, the transfer function was numerically simulated for a reconfigurable MEMS-DSRR hybrid architecture where the DSRR is embedded onto a realistic piezo actuator chip. In this case, a 370 MHz resonance frequency shift was obtained under of a 170 µm extrusion driven by a DC voltage. These characteristics in combination with a high Q factor and dimensions compatible with standard CMOS manufacturing techniques provide a step forward for the production of devices with applications in multiband telecommunications and wireless power transfer and in the IoT field.

On-demand electrical control of spin qubits

Once called a 'classically non-describable two-valuedness' by Pauli, the electron spin forms a qubit that is naturally robust to electric fluctuations. Paradoxically, a common control strategy is the integration of micromagnets to enhance the coupling between spins and electric fields, which, in turn, hampers noise immunity and adds architectural complexity. Here we exploit a switchable interaction between spins and orbital motion of electrons in silicon quantum dots, without a micromagnet. The weak effects of relativistic spin-orbit interaction in silicon are enhanced, leading to a speed up in Rabi frequency by a factor of up to 650 by controlling the energy quantization of electrons in the nanostructure. Fast electrical control is demonstrated in multiple devices and electronic configurations. Using the electrical drive, we achieve a coherence time T2,Hahn ≈ 50 μs, fast single-qubit gates with Tπ/2 = 3 ns and gate fidelities of 99.93%, probed by randomized benchmarking. High-performance all-electrical control improves the prospects for scalable silicon quantum computing.

Nanometer-sized etching of lithium niobate domain wall devices

Ferroelectric LiNbO3 single crystals have piezoelectric, pyroelectric and electro-optic properties and are widely used in nonvolatile memories, sensors, and electro-optic modulators. The material is hard and relatively inert for dying etching using thick Cr/Ni mask layers which are incompatible with the CMOS manufacturing technologies. Moreover, the etching angles are generally below 80° that could result in poor polarization retention and a large imprint effect. Here we developed an etching technique on the basis of the solid-state reaction and wet solution corrosion together that used CMOS-compatible SiO2 masks to fabricate large arrays of LiNbO3 nanodevices in high precision. The LiNbO3 nanopatterns at the regions beyond the SiO2 masks can react with the deposited Al metal below 500 °C in formation of amorphous layers in targeted thicknesses that vary with the annealing temperature and time at a reduced atmosphere. The amorphous layers can be dissolved in mixed solutions of H2O, NH4OH, and H2O2 at 85 °C, and the etching angles of memory cells in lateral sizes of 20–220 nm can approach 90° after the passivation of the LiNbO3 surface layer. The transmission electron microscope study shows the oxygen deficiency at the surface. After the connection of the cell to two side electrodes, domain switching occurs under an applied horizontal electrode field along the polar Z-axis accompanying the formation of conducting domain walls against the peripheral unswitched domain at the substrate. The read current can highly reach the level of 2–20 μA in high reliability. This etching technique promotes the large-scale fabrication of LiNbO3 nanodevices on the Si platform.

57‐3: MircoLED Display Integration on 300mm Advanced CMOS Platform

We show for the first time a microLED display integration flow in a 300mm CMOS manufacturing platform resulting a pixel density of 9150dpi with a 3μm pixel pitch and a brightness for blue μLED in excess of 600kcd/m2 @100A/cm2.

All-optical graphene-on-silicon slot waveguide modulator based on graphene’s Kerr effect

All-optical graphene-based optical modulators have recently attracted much attention because of their ultrafast and broadband response characteristics (bandwidth larger than 100 GHz) in comparison with the previous graphene-based optical modulators, which are electrically tuned via the graphene Fermi level. Silicon photonics has some benefits such as low cost and high compatibility with CMOS design and manufacturing technology. On the other hand, graphene has a unique large nonlinear Kerr coefficient, which we calculate using graphene's tight-binding model based on the semiconductor Bloch equations. Its real and imaginary parts are negative at the wavelength of 1.55 µm and EF=0.1eV. To simultaneously use the benefits mentioned above, we present an all-optical, CMOS-compatible, and graphene-on-silicon slot (GOSS) waveguide extinction and phase modulator that consists of two different geometries. The first one consists of a one-stage GOSS waveguide with a single layer of graphene. To increase the light-graphene interaction and consequently enhance the modulation efficiency (ME), another stage of the GOSS waveguide is placed over the first one. This two-stage configuration is called a graphene-on-silicon double-slot (GOSDS) waveguide. The ME, insertion loss (IL), and modulation depth (MD) for a 12.5 µm GOSDS waveguide modulator with a double layer of graphene can reach 0.241 dB/µm, 1.31 dB, and 77%, respectively, at optical pump intensities about 9MWcm-2. Our design has a smaller waveguide length (17.6 times) than the previous all-optical graphene-on-silicon ribbon waveguide extinction modulator and high MD (about 2 times) in comparison with a graphene-clad microfiber all-optical extinction modulator. Compared with an all-optical Mach-Zehnder interferometer phase modulator, our design has short graphene coated waveguide length (≈0.1 times) and low local optical intensities (≈0.043 times) needed for π phase shift. This study may promote the design and realization of high-performance, wideband, compact, and all-optical control on a single chip with a reasonable contrast level.

A novel ultra-low-power CNTFET and 45 nm CMOS based ternary SRAM

This paper presents a CNTFET based ultra-low-power ternary SRAM design which consumes merely 66 nW of power, achieving 84–98% reduction in power consumption as compared to the other CNTFET ternary SRAM designs reported in the literature. The 6-Transistor (6T) Standard Ternary Inverter (STI) cell or the 3T-STI cell form the basic building block of the conventional SRAM cells. These conventional STI designs have an undesirable direct path between VDD and ground during certain ternary input signals, resulting in higher power consumption. In this paper, a highly power-efficient 4T-STI based Ternary SRAM design is presented, which prevents a direct path between the power supply VDD and ground in all the possible ternary logic states.While CNTFET is preferred by many researchers around the world for low-power VLSI applications, CMOS technology is still widely used in the industry because of the availability of advanced CMOS manufacturing units. Therefore, the proposed ultra-low-power ternary SRAM design has been implemented with both 32 nm CNTFET and 45 nm CMOS devices. The performance of both the CNTFET and CMOS based ultra-low-power ternary SRAM circuits have been benchmarked with corresponding conventional SRAM circuits. The overall decrease in Power Delay Product (PDP) is 86–97% in the proposed ultra-low-power ternary 32 nm CNTFET SRAM circuit and 87–99% in the proposed 45 nm CMOS SRAM with respect to corresponding conventional ternary SRAM circuits.

MSB-split VCM-based charge recovery symmetrical switching with set-and-down asymmetrical switching method for dual-capacitive arrays SAR ADC

With the advanced development of CMOS manufacturing process, the capacitive-array in the successive approximation register analog-to-digital converters (SAR ADCs) has become the dominant source of energy consumption and silicon area. This requires an immediate attention to design a more energy-efficient capacitive switching method while maintaining excellent linearity and noise rejection. A hybrid switching method is proposed for the SAR ADC with dual-capacitive arrays architecture, which consists of MSB-split $$V_{CM}$$ -based charge recovery symmetrical switching and set-and-down asymmetrical switching methods for the coarse and fine resolution conversions, respectively. As a result, it has achieved 99.53% switching energy reduction and 73.44% area reduction compared to the conventional switching method.

An ultra-low-power CNFET based dual VDD ternary dynamic Half Adder

This paper presents an ultra-low-power ternary dynamic Half Adder (HA) design which consumes merely 83 nW of power, achieving a 66–90% reduction in power consumption as compared to the other designs reported in the literature. Conventional ternary circuit designs use single VDD power supply, which is not a power-efficient technique. In these designs, the intermediate ternary logic state (VDD/2) is generated by allowing a steady-state current through two diode-connected transistors connected in series and the output is obtained from the junction of the two transistors. The proposed dual-VDD HA design utilizes both the available ternary power supply voltages (VDD &VDD/2) and prevents direct path between the power supplies and ground, in all the three possible ternary logic output states, resulting in a significant reduction in power consumption.While Carbon Nanotube FETs (CNFETs) is preferred by many researchers around the world for low-power VLSI applications, CMOS technology is still widely used in the industry because of the availability of advanced CMOS manufacturing units. Therefore, the proposed dual-VDD ternary dynamic HA design has been implemented with both CNFET and 45 nm CMOS devices. The proposed CNFET HA has an average delay of merely 8.4 ps, which is lower than the delays experienced in conventional designs (16.5–60.5 ps). The overall decrease in Power Delay Product (PDP) is 72–98% in the proposed CNFET HA, with respect to the other designs reported in the literature.

Improvement of Ferroelectricity and Fatigue Property of Thicker HfxZr1−XO2/ZrO2 Bi-layer

HfxZr1−xO2 (HZO) has been an attractive material for future ferroelectric memory devices because of their high scalability ~10 nm, stable ferroelectricity over a wide Hf:Zr composition range, and compatibility with CMOS manufacturing process. [1] Considering the ferroelectric device manufacturing, the stable ferroelectricity in the thicker film region is required. However, it has been reported that the ferroelectricity of HZO films is generally degraded in the thick ferroelectric film region > 10 nm. [2] To obtain the superior ferroelectricity in the thicker film region, we pay attention to the ferroelectricity of the HZO based thick ferroelectric structures (> 20 nm) with paraelectric HfO2 and anti-ferroelectric ZrO2 layers. In this work, we studied the ferroelectricity and fatigue properties of the thick HZO/ZrO2 and HZO/HfO2 stack structures fabricated using atomic layer deposition (ALD).The TiN/HZO/ZrO2/TiN capacitors were fabricated as follows: An HZO layer was deposited on TiN bottom electrode by ALD at 300 °C using (Hf/Zr)[N(C2H5)CH3]4 (Hf:Zr = 1:1) cocktail precursor and H2O gas. The thickness of the HZO layer were varied from 0 to 10 nm. Next, a 10-nm-thick ZrO2 layer was deposited at 300 °C using (C5H5)Zr[N(CH3)2]3 and H2O gas. After fabrication of HZO/ZrO2 bi-layer, post deposition annealing (PDA) was performed at 600 °C for 1 min in a N2 atmosphere. Finally, TiN top electrode was fabricated by DC sputtering. The capacitors with HZO single layer and HZO/HfO2 bi-layer were also prepared as references.Figure 1 shows the remanent polarization (2P r) of the HZO single layer, HZO/HfO2, and HZO/ZrO2 bi-layers from polarization-electric field (P-E) hysteresis curves as a function of the HZO thickness while the HfO2 and ZrO2 thicknesses were kept at 10 nm. The maximum 2P r (12 µC/cm2) of the HZO single layer was obtained when the thickness of the HZO layer was 10 nm. However, the 2P r of the HZO single layer gradually decreased with the HZO thickness due to the formation of the stable monoclinic phase which shows paraelectricity. [2] The ferroelectric properties of ZrO2 and HfO2 single layers were hardly observed because both layers exhibited anti-ferroelectricity and paraelectricity, respectively. The HZO/HfO2 bi-layer maintained extremely small 2P r regardless of the HZO thickness. On the other hand, the switching properties of HZO/ZrO2 bi-layer were divided into three regions such as anti-ferroelectricity in less than 12.5 nm, mixing phases of anti-ferroelectricity and ferroelectricity in 15 nm, and ferroelectricity in over 17.5 nm. The maximum 2P r of 11 µC/cm2 could be obtained in the 20-nm-thick of HZO/ZrO2 bi-layer, and was approximately 2 times larger than that (6 µC/cm2) of the 20-nm-thick HZO single layer. This superior ferroelectricity of the HZO/ZrO2 bi-layer may be due to the improvement of quality of the HZO layer and the transformation from anti-ferroelectric to ferroelectric phase in the ZrO2 layer. [3, 4]Figure 2 shows endurance properties of HZO (10 nm) single layer, HZO/ZrO2 (20 nm), and HZO/HfO2 (20 nm) bi-layers using positive-up negative-down (PUND) method. For the HZO single layer and the HZO/ZrO2 bi-layer cases, the wake-up effect was observed until 104 cycles, while the HZO/HfO2 bi-layer had small 2P r in the entire switching cycle region. The large difference of 2P r properties between the HZO layer and the HZO/ZrO2 bi-layer was observed in over 104 cycles. Noted that the HZO/ZrO2 bi-layer was larger 2P r than that in pristine condition after 106 cycles, while the 2P r of the HZO single layer was dropped by around 30%. Therefore, it is thought that ZrO2 layer play an important role in preventing the HZO/ZrO2 bi-layer from the degradation of ferroelectricity.In conclusion, the thick HZO/ZrO2 bi-layer exhibited superior ferroelectricity and endurance properties compared to the HZO/HfO2 bi-layer and thin HZO single layer. Based on these results, the HZO/ZrO2 bi-layer using the combination of HZO and ZrO2 layers is one of the promising structures for future ferroelectric devices application.This study was partially supported by JSPS KAKENHI (JP18J22998 and K4H002). The authors thank all staff members of the Nanofabrication Group of NIMS for their support in fabricating the MFM capacitors.[1] J. Müller et al., Nano Lett. 12, 4318 (2012).[2] M. H. Park et al., Appl. Phys. Lett. 102, 242905 (2013).[3] T-.Y. Hsu et al., Smart Mater. Struct. 28, 084005 (2019).[4] S. Shibayama et al., Jpn. J. Appl. Phys. 59, SMMA04 (2020). Figure 1

Exploring Inherently Selective Plasma Processing of Nitrides and Oxides Via Hollow-Cathode Plasma-Assisted Atomic Layer Deposition

Area-selective atomic layer deposition (AS-ALD) is an emerging field of research attracting accelerating interest from the CMOS materials and device research community. The continuing down-scaling in logic and memory field-effect transistor devices along with the increasing three-dimensional structural complexity brings new patterning and processing challenges. With the long-awaited adoption of extreme-UV (EUV) lithography, the escalating stress on precision patterning has decreased, however, alternative self-aligned processing solutions are always highly needed to reduce the number of lithography/deposition/etching steps. AS-ALD, therefore, provides a unique opportunity towards simplifying critical process steps where surface-selective and/or conformal material deposition with sub-nanometer thickness precision is required.Being introduced in the early years of the 21st century, during the early adoption of ALD-grown high-k dielectrics in the CMOS manufacturing industry, significant progress has been made in developing alternative routes for AS-ALD of various oxide and nitride compounds, as well as elemental metallic films. Nucleation/growth inhibition on various surfaces including Si, oxide, nitride, and metal substrates have been explored extensively. The most promising results have been achieved via various self-assembled monolayers (SAMs), which serves as the masking layer to protect the non-growth surface and can be removed with relative ease after ALD process has been completed. Despite successful results for a set of materials grown via conventional thermal-ALD, SAMs are not compatible with plasma-ALD processes, mainly because their soft organic structure which is easily etched under energetic plasma exposure. Therefore, there is a significant need to develop alternative AS-ALD strategies for materials which require the utilization of energetic plasmas for their deposition.While certain nitride materials necessitate the usage of various nitrogen plasmas including III-nitrides for their self-limiting growth at low substrate temperatures, plasma-assistance helps oxides as well in lowering their deposition temperatures and improving physical properties of the films. Previously, we have reported extensively on the self-limiting plasma-assisted ALD (PA-ALD) of crystalline III-nitride films within a common substrate temperature window of lower than 250 °C. In this study, we explore the feasibility of developing area-selective deposition recipes for nitride and oxide compounds via inherently selective nucleation/growth behavior on different surfaces.Our initial results belong to two oxide (Ga2O3 and VOx) and one nitride (BN) binary compound films, all deposited in the same PA-ALD system featuring a large-diameter hollow-cathode plasma source. Ga2O3, VOx, and BN films were deposited using triethylgallium (TEG), TEMAV, and triethylboron (TEB) as metal precursors, respectively, while Ar/O2 and Ar/N2 plasma were used as oxygen and nitrogen co-reactants, respectively. Growth experiments have been performed at 200 °C substrate temperature and within 50 – 100 W rf-power range. Real-time in-situ ellipsometry was used to closely monitor the individual growth reactions taking place on the surface, depicting metal precursor chemisorption and plasma-assisted ligand removal/exchange reactions. 30-cycle deposition runs on three different substrate surfaces (solvent-cleaned Si, BOE-cleaned Si, and solvent-cleaned Al2O3) were in-situ monitored for the detection of any nucleation inhibition or growth retardation.Our initial results show that inherent surface selectivity in PA-ALD growth of VOx and BN films on Si vs. Al2O3 substrates can be achieved. Our in-situ ellipsometry results indicate nucleation inhibition behavior of up to 15 ALD cycles for BN on Al2O3 surfaces, when compared to almost no retardation on both Si substrates. Moreover, we also observed that pre-deposition surface plasma treatments result in significantly different growth rates on Si surfaces, with the fastest growth occurring on non-plasma treated surfaces. Pretty similar results were obtained for VOx films, showing a rather significant nucleation delay of at least 25 cycles on Al2O3 surfaces, while plasma-treated Si surfaces show differences in growth behavior. These initial results confirm indeed the feasibility of achieving selective plasma processing, despite the known rather unselective behavior of energetic plasmas. We attribute these initial promising results to the radical-rich content of our hollow-cathode plasma which most probably shows more surface chemistry dependence when compared to ion-rich plasmas. We’ll present ex-situ material characterization data of thicker films along with possible routes to obtain desired higher selectivity values. Figure 1

LPC: An Error Correction Code for Mitigating Faults in 3D Memories

The radiation sensitivity of memory cells increases dramatically as CMOS manufacture technology scales down; therefore, the reliability of memories has become a challenge. 3D technology has gained attention for having several advantages compared to the 2D counterpart, such as high integration density, high performance, low power, and high communication speed. Although several studies are targeting 3D memories, the effects on reliability using this technology have received little attention. This work introduces Line Product Code (LPC), a modified product code-based Error Correction Code (ECC) that uses both Hamming and parity in both rows and columns to implement reliable 3D memories. We implemented two lightweight LPC-based decoding algorithms in interleaved (LPCa-I) and non-interleaved (LPCa) versions, which allowed us to analyze LPC through a set of simulation cases that considers four severity levels of error incidence. The experimental results showed the effectiveness of the LPC-based algorithms, reaching correction rates of up 2.3 times higher compared to other Hamming-based algorithms.

Direct Wafer Bonding Methods: A Practical Process Selection Guide

The development of various low temperature wafer bonding methods in early 2000’s marked an important milestone for the direct wafer bonding applications. Wafer bonding was adopted in the microelectronics fabs as the use of plasma activated wafer bonding allowed for meeting the CMOS manufacturing requirements in terms of contamination control as well as thermal budget limitations (less than 400°C).A wafer bonding technique reported in the literature already in late 80’s – early 90’s allowed even for room temperature bonding of some materials but despite this important feature it remained mainly at the fundamental research level, with not so numerous applications in semiconductor industry. This technique is known mainly as “surface activated bonding”, “SAB” or “room temperature covalent bonding”. Over the past decade, the interest in surface activated bonding increased significantly as excellent results were reported particularly for compound semiconductors applications (e.g. solar cells manufacturing, power devices, etc.). With three types of direct wafer bonding processes, high, low and room temperature, sometimes people are facing issues in selecting the proper wafer bonding process. Our goal in this presentation is to introduce the specific features of each technique and present their benefits with applications examples. Technical as well as cost – related benefits will be emphasized.An overview of the main metrology methods used traditionally for wafer bonding-based applications, as well as new methods adopted based on newest applications fields will be presented.