CMOS Inverter Research Articles

Performance investigation of stacked-channel junctionless Tri-Gate FinFET 8T-SRAM cell

Junctionless FinFET devices are a substitute for conventional FinFET devices due to their short channel effects and easy manufacturing at sub 22 nm technology node. The manuscript presents an 8T-SRAM cell based on tri-gate junctionless FinFET technology. The FinFET device is designed with source/drain of Si material and the channel as a stack of Si − Si 0.75 Ge 0.25 − Si. The proposed SRAM cell structure consists of a CMOS inverter with stacked p-FinFETs, improving its performance in terms of noise margin and leakage power consumption. The manuscript investigates the variation of Static Noise Margin (SNM), leakage power dissipation and delay with supply voltage to analyze the sub-threshold operation of SRAM cell. The results reveal that the cascaded p-FinFETs minimize the leakage current owing to the stack effect, resulting in improved noise margin and lower leakage power. The stacked p-FinFET devices based SRAM cell achieves 1.11x read noise margin, 1.11x hold noise margin, −1.08x write noise margin and 57.1% less leakage power compared to conventional SRAM cell at 1.0 V. However, it exhibits more delay due to increased resistance and capacitance of the cascaded transistors. The process variation analysis is also performed to investigate the SNM distribution using monte-carlo simulation by taking 10,000 samples. The results indicate that the SRAM cell structures provide higher than 6σ yield at range of supply voltages.

Enhancement-Mode Ambipolar Thin-Film Transistors and CMOS Logic Circuits using Bilayer Ga2O3/NiO Semiconductors.

Recent advancements in power electronics have been driven by Ga2O3-based ultrawide bandgap (UWBG) semiconductor devices, enabling efficient high-current switching. However, integrating Ga2O3 power devices with essential silicon CMOS logic circuits for advanced control poses fabrication challenges. Researchers have introduced Ga2O3-based NMOS and pseudo-CMOS circuits for integration, but these circuits may either consume more power or increase the design complexity. Hence, this article proposes Ga2O3-based CMOS realized using heterogeneous 3D-stacked bilayer ambipolar transistors. These ambipolar transistors consist of HfO2/NiO/Ga2O3/NiO/HfO2 heterostructures that are wrapped around by the Ti/Au gate electrode, resulting in record high electron and hole current on/off ratios of 109 and 107. The threshold voltage, subthreshold swing, and current density measured from 100 ambipolar devices (across 5 batches) are around -7.99 ± 0.92 V (p-channel) and 7.81 ± 0.81 V (n-channel), 0.59 ± 0.07 V/dec (p-channel) and 0.61 ± 0.06 V/dec (n-channel), and 0.99 ± 0.26 mA/mm (p-channel) and 58.23 ± 12.99 mA/mm (n-channel), respectively. All the 100 ambipolar devices showed decent long-term stability over a period of 200 days, exhibiting reliable electrical performance. The threshold voltage shift (ΔVTH) after negative bias stressing for a period of 3500 s is around 11.52 V (p-channel) and 10.21 V (n-channel), respectively. Notably, the n-channels exhibit ∼2 orders higher on/off ratio than the best Ga2O3 unipolar transistors at 300 °C. Moreover, the polarities of ambipolar transistors are reconfigurable into p- or n-MOS, which are integrated to demonstrate CMOS inverter, NOR, and NAND logic gates. The switching periods from "0" to "1" and from "1" to "0" of NOR are 0.12 and 0.17 μs, and those of NAND are 0.16 and 0.13 μs. This work lays the foundation of oxide-semiconductor-based CMOS for future integrated electronics.

Quantum and classical simulation of core shell based junctionless field effect transistor with digital application

The detailed performance analysis of core–shell Gate All Around junctionless field effect transistor along with CMOS inverter as an application with quantum models is presented in this paper for the first time. To appreciate the performance of the device and the application even at smaller channel length, the comparison with classical models is also presented. The OFF current was calculated as 3.68 × 10−16A on incorporating the quantum models. The subthreshold swing (SS) and Drain induced barrier lowering (DIBL) are found to be near ideal values. The SS and DIBL was calculated as 62.82 mV/dec and 33.4 mV/V. The DIBL was found to be lesser by 52.82% with quantum model than classical model. The performance obtained using quantum models are better than the classical models in terms of different parameters such as OFF current, ON current, SS, DIBL, threshold voltage, transconductance. Further, the performance of the CMOS inverter with quantum models by considering the n-type and p-type core–shell Gate All Around junctionless field effect transistor is also presented . The OFF current of p-type and n-type was matched before designing the application. A sharp transfer characteristics of the CMOS inverter is obtained. The performance was also studied by calculating the drain current from each of p-type and n-type and found to be more than 1 × 10−7A and SNM (Static Noise Margin) was calculated as 267 mV. The transient response of CMOS inverter exhibits the potential of CMOS inverter using the proposed device even at smaller channel lengths.

Realization of MoTe2 CMOS inverter by contact doping and channel encapsulation

The Fermi level pinning effect significantly limits the application of electrical devices based on two-dimensional materials like transition metal dichalcogenide. Here, a CMOS inverter, which is comprised of an n- and a p-MoTe2 FET with optimized properties, has been successfully fabricated by using contact doping and channel encapsulation methods. Contact doping is to control the polarity of MoTe2-FET and improve contact properties, which is achieved by laser irradiation in different environmental conditions. The channel of two MoTe2-FETs was encapsulated by hexagonal boron nitride (h-BN) to enhance carrier mobility and device stability. The fabricated CMOS inverter showed a very high gain value of 31 at V dd = 4 V at RT.

Exploring the Suitability of Stacking Devices in a Vertical Nanowire to Implement a CMOS Inverter

Exploring the Suitability of Stacking Devices in a Vertical Nanowire to Implement a CMOS Inverter

Fifty Applications of the CMOS Inverter—Part 1 [The Analog Mind]

Fifty Applications of the CMOS Inverter—Part 1 [The Analog Mind]

Explicit Function Model of Electromagnetic Reliability for CMOS Inverters Under HPM Coupling Based on Physical Mechanism Analysis and Neural Network Algorithm

Explicit Function Model of Electromagnetic Reliability for CMOS Inverters Under HPM Coupling Based on Physical Mechanism Analysis and Neural Network Algorithm

Jitter due to Random Telegraph Noise: a Study on the Time Dependent Variability of a Ring Oscillator

Random Telegraph Noise is a relevant source of variability in integrated circuits and a growing issue due to device scaling. Jitter is one of its consequences; therefore, it is an important parameter of performance measurements for electronic components and systems. In this paper, the relationship between Random Telegraph Noise and different concepts of jitter is studied. Firstly, a gate delay variability study of a CMOS inverter is discussed. Then, an absolute, a periodic, and a cycle-to-cycle jitter are evaluated in a five-stage ring oscillator. All the data were generated with a spice simulator modified to properly account for Random Telegraph Noise, using the Monte Carlo technique.

A CMOS inverter from stacked ribbons

A CMOS inverter from stacked ribbons

An Improved Model of Single-Event Transients Based on Effective Space Charge for Metal-Oxide-Semiconductor Field-Effect Transistor.

In this paper, a single-event transient model based on the effective space charge for MOSFETs is proposed. The physical process of deposited and moving charges is analyzed in detail. The influence of deposited charges on the electric field in the depletion region is investigated. The electric field decreases in a short time period due to the neutralization of the space charge. After that, the electric field increases first and then decreases when the deposited charge is moved out. The movement of the deposited charge in the body mainly occurs through ambipolar diffusion because of its high-density electrons and holes. The derivation of the variation in electric field in the depletion region is modeled in the physical process according to the analysis. In combination with the ambipolar diffusion model of excessive charge in the body, a physics-based model is built to describe the current pulse in the drain terminal. The proposed model takes into account the influence of multiple factors, like linear-energy transfer (LET), drain bias, and the doping concentration of the well. The model results are validated with the simulation results from TCAD. Through calculation, the root-mean-square error (RMSE) between the simulation and model is less than 3.7 × 10-4, which means that the model matches well with the TCAD results. Moreover, a CMOS inverter is simulated using TCAD and SPICE to validate the applicability of the proposed model in a circuit-level simulation. The proposed model captures the variation in net voltage in the inverter. The simulation result obviously shows the current plateau effect, while the relative error of the pulse width is 23.5%, much better than that in the classic model. In comparison with the classic model, the proposed model provides an RMSE of 7.59 × 10-5 for the output current curve and an RMSE of 0.158 for the output voltage curve, which are significantly better than those of the classic model. In the meantime, the proposed model does not produce extra simulation time compared with the classic double exponential model. So, the model has potential for application to flow estimation of the soft error rate (SER) at the circuit level to improve the accuracy of the results.

A low power varactor based digitally controlled oscillator design in 180 nm CMOS technology

This paper reports two distinct architectures for digitally-controlled oscillators (DCOs) utilizing MOS varactor, designed in TSMC 180 nm CMOS technology. The first DCO design employs a CMOS inverter, while the second design features a Three-Transistors (3T) NAND gate as a delay stage inverter. Using these delay stages, three-bit, five-bit, and seven-bit controlled DCO circuits have been designed. For the inverter-based DCO circuit, the frequency spans from 4.844 to 2.708 GHz, 2.523 to 0.853 GHz, and 1.364 to 0.253 GHz, with a power consumption of 0.958 mW, 1.597 mW, and 2.236 mW for three-bit, five-bit, and seven-bit DCO variants, respectively. Further, the 3T-NAND gate-based DCO circuit exhibits oscillation frequencies ranging from 2.024 to 0.517 GHz, 0.867 to 0.131 GHz, and 0.341 to 0.033 GHz, with the resulting power consumption of 0.335 mW, 0.559 mW, and 0.782 mW. Equally significant, the proposed inverter-based DCO attains phase noise of − 102.61 dBc/Hz@1MHz, − 99.65 dBc/Hz@1MHz, and − 117.54 dBc/Hz@1MHz, accompanied by corresponding figures of merit (FoM) 174.94 dBc/Hz, 161.27 dBc/Hz, and 165.10 dBc/Hz for three-bit, five-bit, and seven-bit control words, respectively. For the 3T-NAND gate-based DCO, phase noise levels register at − 93.51 dBc/Hz@1MHz, − 113.07 dBc/Hz@1MHz, and − 106.96 dBc/Hz@1MHz, with FoM values of 160.23 dBc/Hz, 166.70 dBc/Hz, and 150.30 dBc/Hz for three-bit, five-bit, and seven-bit DCO variants, respectively. The comprehensive analysis of the proposed DCOs demonstrates the power supply variations, phase noise deviations, and frequency variations. The reported DCOs perform better with regard to output frequency range, power consumption, and overall FoM.

Design on Formation of Nickel Silicide by a Low‐Temperature Pulsed Laser Annealing Method to Reduce Contact Resistance for CMOS Inverter and 6T‐SRAM on a Wafer‐Scale Flexible Substrate

AbstractA pulsed laser annealing method is utilized to directly synthesize nickel silicide (NiSi) as a contact material to improve the contact of electric devices. Three laser wavelengths, 355 nm (ultraviolet laser), 532 nm (green laser), and 1064 nm (infrared laser), are used for the NiSi synthesis during the pulsed laser annealing process. A NiSi phase with low sheet resistance is formed by an ultraviolet laser annealing (ULA) process without damaging the polyimide (PI) substrate. With the integration of the ULA process‐induced NiSi into p‐nnel MOSFET (PMOS) and n‐channel MOSFET (NMOS) devices, the on/off ratio improves significantly, and the field‐effect mobility increases by 30% because of the reduction in contact resistance from 21 to 8.5 kΩ. In addition to the PMOS and NMOS, the gains of the CMOS inverter at different Vdd values are improved by at least 30%. Moreover, the static noise margin of 6T‐SRAM is elevated from 0.82 to 1 V at Vdd = 4 V. The ability of the ULA process to synthesize a high‐quality NiSi layer on a flexible substrate is demonstrated. The integration of NiSi into electrical devices offers a new pathway for improving the electrical behavior of flexible devices.

Negative capacitance gate stack and Landau FET-based voltage amplifiers and circuits: Impact of ferroelectric thickness and domain variations

This article analyzes the impact of ferroelectric hafnium zirconium oxide (HZO) thickness (tFE) and domain number (N) variations on the negative capacitance (NC) effect in metal/HZO/metal gate stack and its implications on Landau FET-based device-circuit co-design through simulations. As tFE decreases, the NC effect weakens, resulting in less S-shaped hysteresis loops for charge and polarization versus voltage characteristics. The study highlights the trade-off between energy dissipation and NC effect voltage window in ferroelectric devices and the importance of balancing both. We developed Landau FET-based voltage amplifiers (VA), including passive VA (PVA) and active VA (AVA), and compared to existing counterparts such as P(VDF-TrFE)-PVA and PZT-AVA, across low and high frequencies. The proposed PVA shows a 22.60% and 54.31% increase in amplification (ANC) at low and high frequencies, respectively, compared to P(VDF-TrFE)-PVA. The AVA exhibits a 17.86% increase in ANC at low frequencies compared to PZT-AVA but no ANC at higher frequencies due to symmetry-breaking. The Landau FET-based inverter shows a sharp state transition than the CMOS inverter, but this sharpness depends on tFE, N, and the degree of NC effect. The Landau FET-based fan-out-4 inverter with 7.7 nm tFE and N = 16 is 25.49% faster than the Si MOSFET inverter. Moreover, the impact of tFE and N on the performance of the proposed 5-stage ring oscillator (RO) is investigated concerning state-of-the-art CMOS RO counterparts. The 5-stage RO using Landau FET-based inverters showed (1.26–18.9) times higher oscillation frequency (fOSC) and (17.93–5.71) times reduced power dissipation compared to the existing CMOS ROs. Finally, we examined how process variations impact the fOSC in the proposed 5-stage Landau FET-based RO. The findings indicate a standard deviation of 0.39 GHz in the distribution of fOSC. These findings highlight the interplay between tFE scaling, N variations, and transient NC effect, advancing Landau FET-based devices for future NC electronics.

Prediction of variation aware FOSC in ring oscillators (ROs) to mitigate the impact of aging on RO-PUF

We propose a methodology to predict device-level variability (including aging) impact on the oscillation frequency (Fosc) of an N-stage ring oscillator (RO). This task is accomplished by creating a tool in a Python environment that uses our own developed variability-aware timing models of the CMOS inverter. Moreover, we use the model to foretell the impact of aging on the logical effort (g) of a CMOS inverter. Using the modified g, we resize ROs in an RO-based physical unclonable function (PUF) in the pre-layout stage to mitigate the impact of aging on the reliability of RO-PUF. The simulation is performed in the Cadence AMS environment using STMicroelectronics (STM) 28 nm CMOS process technology. With a one-time SPICE/aging simulation, the proposed methodology eliminates SPICE/aging simulation overhead for the prediction of variability impact on Fosc of a given N-stage RO. This approach mitigates the impact of aging on the reliability of RO-PUF and provides a method for variability (including aging) aware design in the pre-layout stage.

Bismuth sulfide based resistive switching device as the key to advanced logic gate fabrication

A memristor is a two-terminal electrical component with the scope of future computing applications and analog electronics. In this report, bismuth sulfide decorated one-dimensional carbon nitride nanotube was synthesized and characterized with various analytical techniques. The electrical property of the synthesized material was measured using a two-terminal metal–insulator–metal type of device that exhibited the resistive switching characteristics with the ON to OFF ratio of 2 × 103. The electron transport mechanism of the device was followed by Schottky emission and Poole–Frenkel emission for a low conductance state and Ohmic conduction behavior at the high conductance state. A decrease in the trap depth was identified in the simulation study with increasing applied potential and that supported the proposed mechanism. Read endurance and retention behavior of the device are stable in nature, supported by the statistical analysis. Furthermore, a hybrid logic gate was designed using two identical memristors, one CMOS inverter, one resistor, one voltage divider, and a buffer gate. The designed logic gate exhibited stable nand and nor gate operation based on the control signal.

The method of reducing the CMOS inverter switching energy

The method of reducing the CMOS inverter switching energy

Charge-plasma-based inverted T-shaped source-metal dual-line tunneling FET with improved performance at 0.5 V operation

In this paper, a charge plasma-based inverted T-shaped source-metal dual line-tunneling field-effect transistor (CP-ITSM-DLTFET) has been proposed to improve the ON current (ION) by increasing the line-tunneling area. In the proposed structure, the charge plasma technique is used to induce the dopants in the source and drain regions. Due to its doping-less structure, the proposed CP-ITSM-DLTFET is immune to random dopant fluctuations and does not require an expensive thermal annealing technique. This makes the proposed device’s fabrication easier and more efficient. The proposed CP-ITSM-DLTFET comprises an inverted T-shaped source metal (sandwiched between the Si-channel) and creates gate-to-source overlap and increases the tunneling area vertically on both sides of the Si-channel. The vertical line-tunneling area in the proposed structure makes the device able to be aggressively scaled compared to conventional TFETs for future technology. The proposed CP-ITSM-DLTFET outperforms almost all pre-existing dopingless TFETs in terms of DC and RF parameters. The switching performance (like high ION = 31.88 uA um−1, steeper AVSS = 23.42 mV dec−1 (over 12-order of drain current), and high ION/IOFF ratio of 1.6 × 1013) and the RF performance (like transconductance (gm) = 0.37 mS, Cut-off frequency (fT) = 90.18 GHz, and Gain Bandwidth product (GBW) = 32.3 GHz) of the proposed CP-ITSM-DLTFET are superior to almost all pre-existing Si, SiGe, and Ge based doping-less TFETs. Moreover, the proposed CP-ITSM-DLTFET-based CMOS inverter has also been comprehensively studied in the paper, showing a good noise margin NMH = 0.198 V (39.8% of VDD) and NML = 0.206 V (41.2% of VDD) with a high voltage gain of 30.25 at VDD = 0.5 V, suggesting great potential for future low power applications.

Enhanced Stability of SiZTO TFT Under Positive Voltage and Light Negative Voltage Stress and Modified Hysteresis of the CNTs/SiZTO CMOS Inverter by Si Doping

Enhanced Stability of SiZTO TFT Under Positive Voltage and Light Negative Voltage Stress and Modified Hysteresis of the CNTs/SiZTO CMOS Inverter by Si Doping

Design optimization of junctionless bottom spacer tapered FinFET: Device to circuit level implementation

This manuscript for the first time integrates the traditional FinFET architecture involving Bottom spacer (BS), Tapering, and Junctionless (JL) concepts to investigate the device analog/RF performance at sub- 5 nm technology node. Initially, to come up with an optimal BS and Fin angle (θ), a variation in these values is performed and found that higher θ and lower HBS would be the best fit to optimize the device performance. Following this, a variation in gate length (Lg) is rendered amidst 8 nm–14 nm and noticed that least Lg would be preferable for some parameters sacrificing other parameters which depends upon the application requirement. Later, at fixed Lg, fin angle (θ) variations (80°–87°) are performed to observe the analog/RF performance and noticed that higher θ fetched better performance. Further, at this optimal Lg and θ, height of the Bottom spacer (HBS) is varied between 5 nm–25 nm to inspect the device characteristics and least HBS must be preferred. At last, the dielectric material of BS is changed (SiO2, Si3N4, HfO2) to observe if the material is showing any impact on the device and noticed that replacement of lower dielectric materials with higher dielectric materials is not a bad idea and delivers excellent performance by optimally choosing dielectric values. Further the CMOS inverter performance is also examined. The flow of this manuscript is arranged in such a way that it provides a complete flavour to the design engineers in choosing the best electrical/analog/RF and circuit performance of JL - BS - Tapered FinFET.

Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort

A static timing analysis (STA) methodology based on an effective current source model (ECSM) is proposed for the first time for estimating the aging aware path-level timing performance and its impact on the logical effort of a CMOS inverter for digital timing closure in pre-stress and post-stress conditions. Degradation in the threshold voltage (Vth) of PMOS occurs due to temporal variability mechanisms (aging), such as negative bias temperature instability, resulting in delay degradation of a standard cell. Therefore, we proposed a technique to make the STA process aware of this degradation by developing device-level variation aware (with aging) timing models of CMOS inverters to represent threshold-crossing points (TCPs) in an ECSM.libs file as a function of stress time (t). A device-level approach for Vth degradation into different aging conditions, such as static and dynamic, is developed for a given process design kit to update TCPs in a (.libs) file as a function of t. A python-based tool is being developed to estimate the path-level timing performance of digital circuits in pre-and post-stress conditions. Again, we developed a technique for relating the inverter’s logical effort with t to resize a near-critical path in pre-stress conditions for achieving digital timing closure in pre-and post-stress conditions. The verification and validation of the proposed model with different benchmark circuits are performed using a parasitic extracted netlist in Eldo SPICE environment with 65 nm CMOS process technology. Finally, our model reduces the number of SPICE/Stress simulations by 98.13% compared to the previously reported only simulation-based techniques.