Clocking Scheme Research Articles

A Digital Baseband with Novel Clock Generator for UHF RFID Tag

Clock accuracy is critical to the performance of UHF (Ultra High Frequency) RFID (Radio Frequency Identification) tag, especially for the encoder in baseband. To reduce the bit error rate of the responded data from tag, a novel clock strategy is proposed in this paper, which generates a high accuracy clock for the encoder by counting the preamble of the commands from reader. Moreover, for reducing the chip area and the power consumption, a novel CRC (Cyclic Redundancy Check) generator is designed, which reuses the resource and fulfills a no-gap-link between the responded data and CRC code. The baseband of tag is implemented in a 0.18μm CMOS process and its area is 75479μm.Simulation results show that the frequency variation of the clock is within a reasonable range. 

Ethernet transport system supporting delay‐sensitive real‐time traffics

SUMMARYWe propose and demonstrate an Ethernet transport system that can support hard real‐time traffics with guaranteed throughput and very low jitter performance even in the presence of asynchronous traffics. The superframe structure‐based Ethernet system first synchronizes all the nodes in a network by using the IEEE 1588‐compliant boundary clock scheme and then reserves the traffic channels for synchronous traffics before accommodating both synchronous and asynchronous traffics in the superframe. Our experimental demonstration performed on field‐programmable gate array‐enabled Gigabit Ethernet test benches shows that the proposed scheme not only guarantees the throughput of the synchronous frames but also substantially reduces the jitter of the synchronous frames less than 110 ns after seven‐hop transmission. Copyright © 2013 John Wiley & Sons, Ltd.

Two-Phase RTD-CMOS Pipelined Circuits

MOnostable-BIstable Logic Element (MOBILE) networks can be operated in a gate-level pipelined fashion (nanopipeline) allowing high through output. Resonant tunneling diode (RTD)-based MOBILE nanopipelined circuits have been reported using different clock schemes including a four-phase strategy and a single-phase clock scheme. In particular, significant power advantages of single-phase RTD-CMOS MOBILE circuits over pure CMOS have been shown. This letter compares the RTD-CMOS realizations using a single clock and a novel two-phase clock solution. Significant superior robustness and performance in terms of power and area are obtained for the two-phase implementations.

Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains

This article presents a hybrid Automatic Test Pattern Generation (ATPG) technique using the staggered Launch-On-Shift (LOS) scheme followed by the one-hot launch-on-shift scheme for testing delay faults in a scan design containing asynchronous clock domains. Typically, the staggered scheme produces small test sets but needs long ATPG runtime, whereas the one-hot scheme takes short ATPG runtime but yields large test sets. The proposed hybrid technique is intended to reduce test pattern count with acceptable ATPG runtime for multimillion-gate scan designs. In case the scan design contains multiple synchronous clock domains, and each group of synchronous clock domains is treated as a clock group and tested using a launch-aligned or a capture-aligned LOS scheme. By combining these schemes together, we found the pattern counts for two large industrial designs were reduced by approximately 1.6X to 1.8X, while the ATPG runtime was increased by 40% to 50%, when compared to the one-hot clocking scheme alone.

Low Transition Test Pattern Generator Architecture for Built-in-Self-Test

Problem statement: In Built-In Self-Test (BIST), test patterns are generated and applied to the Circuit-Under-Test (CUT) by on-chip hardware; minimizing hardware overhead is a major concern of BIST implementation. In pseudorandom BIST architectures, the test patterns are generated in random nature by linear feedback shift registers. This normally requires more number of test patterns for testing the architectures which need long test time. Approach: This study presents a novel test pattern generation technique called Low-Transition Generalized Linear Feedback Shift Register (LT-GLFSR) with bipartite (half fixed) and bit insertion (either 0 or 1) techniques. Intermediate patterns (by bipartite and bit (either 0 or 1) insertion technique) inserted in between consecutive test patterns generated by GLFSR which is enabled by a non overlapping clock scheme. This process is performed by finite state machine generate sequence of control signals. Low-Transition Generalized Linear Feedback Shift Registers (LT-GLFSR), are used in a circuit under test to reduce the average and peak power during transitions. LT-GLFSR patterns high degree of randomness and correlation between consecutive patterns. LT-GLFSR does not depend on circuit under test and hence it is used for both BIST and scan-based BIST architectures. Results and Conclusion: Simulation results prove that this technique has reduction in power consumption and high fault coverage with minimum number of test patterns. The results also show that it reduces the peak and average power consumption during test for ISCAS’89 bench mark circuits.

Low-Swing Differential Conditional Capturing Flip-Flop for LC Resonant Clock Distribution Networks

In this paper we introduce a new flip-flop for use in a low- swing LC resonant clocking scheme. The proposed low-swing differential conditional capturing flip-flop (LS-DCCFF) operates with a low-swing sinusoidal clock through the utilization of reduced swing inverters at the clock port. The functionality of the proposed flip-flop was verified at extreme corners through simulations with parasitics extracted from layout. The LS-DCCFF enables 6.5% reduction in power compared to the full- swing flip-flop with 19% area overhead. In addition, a frequency dependent delay associated with driving pulsed flip-flops with a low-swing sinusoidal clock has been characterized. The LS-DCCFF has 870 ps longer data to output delay as compared to the full-swing flip-flop at the same setup time for a 100 MHz sinusoidal clock. The functionality of the proposed flip-flop was tested and verified by using the LS-DCCFF in a dual-mode multiply and accumulate (MAC) unit fabricated in TSMC 90-nm CMOS technology. Low-swing resonant clocking achieved around 5.8% reduction in total power with 5.7% area overhead for the MAC.

Readout System With On-Board Demodulation for CMB Polarization Experiments Using Coherent Polarimeter Arrays

B-modes are special patterns in cosmic microwave background (CMB) polarization. The detection of them is a smoking-gun signature of primordial gravitational waves. The generic strategy of the CMB polarization experiments is to employ a large number of polarimeters for improving the statistics. The Q/U Imaging ExperimenT-II (QUIET-II) has been proposed to detect the B-modes using the world's largest coherent polarimeter array (2,000 channels). An unique detection technique using QUIET's polarimeters, which is a modula- tion/demodulation scheme, enables us directly extracting the polarization signal. The extracted signal is free from non- polarized components and intrinsic 1/f noise. We developed a data readout system with on-board demodulation functions for the QUIET-II experiment. We employed a "master" clock strategy. This strategy guarantees phase matching between the modulation by the polarimeters and the demodulation by ADC modules. The single master generates all carrier clocks and distributes them to each module. The developed electronics, clock modules, and the ADC modules fulfill requirements. Tests with a setup similar to that of the real experiment proved that the system works properly. The performance of all system components are validated to be suitable for B-mode measurements.

Low Transition-Generalized Linear Feedback Shift Register Based Test Pattern Generator Architecture for Built-in-Self-Test

Problem statement: In Built-In Self-Test (BIST), test patterns are ge nerated and applied to the Circuit-Under-Test (CUT) by on-chip hardware; minimizing hardware overhead is a major concern of BIST implementation. In pseudorandom BIST architectures, the test patterns are generated in random nature by Linear Feedback Shift Registers. This nor mally requires more number of test patterns for testing the architectures which need long test time . Approach: This study presents a novel test pattern generation technique called Low-Transition Generali zed Linear Feedback Shift Register (LT-GLFSR) and it was also called Bipartite GLFSR. Intermediat e pattern (Bipartite technique) inserted in between consecutive test patterns generated by GLFSR was called LT-GLFSR technique which was enabled by a non overlapping clock scheme. Low-transition generalized linear feedback shift registers (LT-GLFSR), was used in a circuit under test to reduce the aver age and peak power during transitions. LT-GLFSR pattern generator would generate patterns with high er degree of randomness and high correlation between consecutive patterns would have efficient area impl ementation. LT-GLFSR did not depend on circuit under test and hence it could be used for both BIST and scan-based BIST architectures. Results/Conclusion: Simulation results show that this technique has re duction in power consumption and high fault coverage with minimum number of test patterns. The results also show that it reduces th e peak and average power consumption during test for ISCAS'89 bench mark circuits.

Two-layer synchronized ternary quantum-dot cellular automata wire crossings

Quantum-dot cellular automata are an interesting nanoscale computing paradigm. The introduction of the ternary quantum-dot cell enabled ternary computing, and with the recent development of a ternary functionally complete set of elementary logic primitives and the ternary memorizing cell design of complex processing structures is becoming feasible. The specific nature of the ternary quantum-dot cell makes wire crossings one of the most problematic areas of ternary quantum-dot cellular automata circuit design. We hereby present a two-layer wire crossing that uses a specific clocking scheme, which ensures the crossed wires have the same effective delay.

Optimization of Device Clocking Schemes to Minimize the Effects of Radiation Damage in Charge-Coupled Devices

The European Space Agency Euclid mission aims to answer the question of how the universe originated through the mapping of the dark Universe. One method to investigate this geometry is to measure subtle changes in ellipticity using image sensors such as the charge-coupled device (CCD). However, the radiation environment in space plays a major part in the performance of CCD-based camera systems. When placed in space, a CCD becomes damaged by the radiation environment, and this can lead to a “smearing” of the charge, acting to change the ellipticity, and therefore, one must be able to separate the changes in ellipticity caused by radiation damage from those the mission aims to measure. To this end, the radiation-damage-induced shape changes require an in-depth investigation such that optimized operation can be achieved. A Monte Carlo simulation is being used to predict this impact, backed by experimental data from a detector formerly baselined for the mission. During the experimental study, an investigation was undertaken into the serial readout of the CCD to demonstrate an approach toward performance optimization through a consideration of the trap species involved. A change in the clocking scheme was found to result in a factor of 3 reduction in charge transfer inefficiency.

On-Chip Clocking of Nanomagnet Logic Lines and Gates

The nanomagnet logic (NML) devices considered here are variants of proposed components for the edge-driven, quantum-dot cellular automata device architecture, where the position of electrons on quantum dots was suggested as a mechanism for representing binary state. To control NML circuit components (e.g., gates and lines), to date, externally generated magnetic fields have served as a clock. The clock is used to make the magnets in a circuit ensemble transition to a metastable state, so fringing fields from individual devices can set the state of a neighboring device in accordance with a new input. However, such a clocking scheme is obviously not extensible to chip-level systems. For NML to be a viable candidate for digital systems, a mechanism for simultaneously modulating the energy barriers of a group of devices must be implemented “on-chip,” and guarantee unidirectional dataflow from circuit input to circuit output. We have experimentally demonstrated a CMOS-compatible clock, and used it to reevaluate all of the NML constructs required for a functionally complete logic set. All possible input combinations to said constructs were successfully considered. Experiments were designed to promote unidirectional dataflow.

A 1.25 ps Resolution 8b Cyclic TDC in 0.13 $\mu$m CMOS

This paper describes the first implementation of the well-known cyclic ADC architecture into a time-to-digital converter. With an asynchronous clocking scheme, an all-digital 1.5b time-domain multiplying DAC (MDAC) is repetitively used for 8b conversion. The MDAC is based on a 2 × time amplifier with an offset-compensated gain calibration scheme. The proposed cyclic TDC, fabricated in a 0.13 μm CMOS, shows a resolution of 1.25 ps with a total conversion range of ±160 ps, the maximum operating frequency of 100 MHz, and a power consumption of 4.3 mW at 50 MHz. The measured DNL and INL are ± 0.7 LSB and - 3 to + 1 LSB, respectively.

Energy-Efficient Bennett Clocking Scheme for Four-State Multiferroic Logic

Nanomagnets with biaxial magnetocrystalline anisotropy have four stable magnetization orientations that can encode 4-state logic bits (00), (01), (11) and (10). Recently, a 4-state NOR gate derived from three such nanomagnets, interacting via dipole interaction, was proposed. Here, we devise a Bennett clocking scheme to propagate 4-state logic bits unidirectionally between such gates. The nanomagnets are assumed to be made of 2-phase strain-coupled magnetostrictive/piezoelectric multiferroic elements, such as nickel and lead zirconate titanate (PZT). A small voltage of 200 mV applied across the piezoelectric layer can generate enough mechanical stress in the magnetostrictive layer to rotate its magnetization away from one of the four stable orientations and implement Bennett clocking. We show that a particular sequence of positive and negative voltages will propagate 4-state logic bits unidirectionally down a chain of such multiferroic nanomagnets for logic flow.

Reduced-Ripple p-Channel Metal–Oxide–Semiconductor Field-Effect Transistor Charge Pump Circuit with Small Filtering Capacitance

This paper presents a two-stage, two-phase, p-channel metal–oxide–semiconductor field-effect transistor (PMOSFET) charge pump with special two-step clocks for ripple reduction. The ripple voltage can be reduced by adjusting the overdrive voltage during charge transfer. The charge pump including the circuit of the proposed clocks and 5 pF boosting capacitance was fabricated using 0.35 µm complementary metal–oxide–semiconductor field-effect transistor (CMOSFET) technology in an area of 0.182 mm2. With the new clock scheme, high voltage gain and driving capacity without overstress of the transistors are preserved. The experimental results reveal that the output voltage ripple is reduced from 23.2 to 12.8 mV for an output current of 36 µA at a frequency of 10 MHz and a supply voltage of 1.8 V, which indicates a 45% ripple reduction without increasing filtering capacitance.

An Efficient Dual Charge Pump Circuit Using Charge Sharing Clock Scheme

In this paper, the charge pump efficiency is discussed, and a dual charge pump circuit with complementary architecture using charge sharing clock scheme is presented. The proposed charge sharing clock generator is able to recover the charge from parasitic-capacitor charging and discharging, so that the dynamic power loss in the pumping process is reduced by a half. To preserve the overlapping period of the four-phase clock used for threshold cancellation technique, two complementary sets of clocks are generated from the proposed clock generator, and each set feeds a certain branch of the dual charge pump to achieve the between-branch charge sharing. A test chip is fabricated in 0.18µm process, and the area penalty of the proposed charge sharing clock generator is 1%. From the measurement results, the proposed charge pump shows an overall power efficiency increase with a peak value of 63.7% comparing to 52.3% of a conventional single charge pump without charge sharing, and the proposed clock scheme shows no degradation on the driving capability while the output ripple voltage is reduced by 43%.

Domino inspired MOBILE networks

MOBILE networks can be operated in a gate-level pipelined fashion allowing high through-output. If MOBILE gates are directly chained, a four-phase clock scheme is required. A single phase scheme has been recently reported that alternates rising and falling edge-triggered MOBILE gates. A novel two-phase interconnection scheme resembling conventional domino pipelines is proposed and validated. It exhibits advantages in terms of speed with respect to both four-phase and single-phase interconnection schemes. In addition, the new architecture improves logic flexibility regarding the domino pipeline counterpart, since inverting and non-inverting stages can be interspersed.

Accuracy assessment of single and double difference models for the single epoch GPS compass

The single epoch GPS compass is an important field of study, since it is a valuable technique for the orientation estimation of vehicles and it can guarantee a total independence from carrier phase slips in practical applications. To achieve highly accurate angular estimates, the unknown integer ambiguities of the carrier phase observables need to be resolved. Past researches focus on the ambiguity resolution for single epoch; however, accuracy is another significant problem for many challenging applications. In this contribution, the accuracy is evaluated for the non-common clock scheme of the receivers and the common clock scheme of the receivers, respectively. We focus on three scenarios for either scheme: single difference model vs. double difference model, single frequency model vs. multiple frequency model and optimal linear combinations vs. traditional triple-frequency least squares. We deduce the short baseline precision for a number of different available models and analyze the difference in accuracy for those models. Compared with the single or double difference model of the non-common clock scheme, the single difference model of the common clock scheme can greatly reduce the vertical component error of baseline vector, which results in higher elevation accuracy. The least squares estimator can also reduce the error of fixed baseline vector with the aid of the multi-frequency observation, thereby improving the attitude accuracy. In essence, the “accuracy improvement” is attributed to the difference in accuracy for different models, not a real improvement for any specific model. If all noise levels of GPS triple frequency carrier phase are assumed the same in unit of cycles, it can be proved that the optimal linear combination approach is equivalent to the traditional triple-frequency least squares, no matter which scheme is utilized. Both simulations and actual experiments have been performed to verify the correctness of theoretical analysis.

Asynchronous Bypass Channels for Multi-Synchronous NoCs: A Router Microarchitecture, Topology, and Routing Algorithm

Network-on-chip (NoC) designs have emerged as a replacement for traditional shared-bus designs for on-chip communication. As with all current very large scale integration designs, however, reducing power consumption in NoCs is a critical challenge. One approach to reduce power consumption is to dynamically scale the voltage and frequency of each network node or groups of nodes (DVFS). Another approach is to replace the balanced clock tree with a globally-asynchronous, locally-synchronous (GALS) clocking scheme. In both DVFS and GALS designs, the chip as a whole is multi-synchronous. As the NoCs interconnecting those nodes must communicate across these clock domain boundaries, they tend to have high latencies as packets must be synchronized at the intermediate nodes. In this paper, we propose a novel router microarchitecture which offers superior performance with respect to typical synchronizing router designs for multi-synchronous networks. Our approach features asynchronous bypass channels which allow flit traversal of intermediate nodes within the network without the latching or synchronization overheads of typical designs. We also propose a new network topology and routing algorithm that leverage the advantages of the bypass channel offered by our router design. We present a detailed analysis of design decisions which affect the performance of the asynchronous bypass channel network. Our experiments show that our design improves the performance of a conventional synchronizing design with similar resources by up to 26% at low loads and increases saturation throughput by up to 50% for a uniform random traffic.

Partially Reversible Pipelined QCA Circuits: Combining Low Power With High Throughput

This paper introduces an architecture for quantum-dot cellular automata circuits with the potential for high throughput and low power dissipation. The combination of regions with Bennett clocking and memory storage combines the low power advantage of reversible computing with the high throughput advantage of pipelining. Two case studies are initially presented to evaluate the proposed pipelined architecture in terms of throughput and power consumption due to information dissipation. A general model for assessing power consumption is also proposed. This paper shows that the advantages possible by using a Bennett clocking scheme also depend on circuit topology, thus also confirming the validity of the proposed analysis and model.

A 10-bit 30-MS/s successive approximation register analog-to-digital converter for low-power sub-sampling applications

A 10-bit 30-MS/s successive approximation register analog-to-digital converter (ADC), which is suitable for low-power sub-sampling applications, is presented. Bootstrapped switches are used to enhance the sampling linearity at the high input frequency. The proposed ADC adopts a binary-weighted split-capacitor array with the energy efficient switching procedure and includes an asynchronous clock scheme to yield more power and speed-efficiency. The ADC is fabricated in a 65nm complementary metal-oxide-semiconductor technology and occupies an active area of 0.07mm2. The differential and integral nonlinearities of the ADC are less than 0.82 and 1.13 LSB, respectively. The ADC shows a signal-to-noise-distortion ratio of 56.60dB, a spurious free dynamic range of 73.35dB, and an effective number of bits (ENOB) of 9.11-bits with a 2.5-MHz sinusoidal input at 30-MS/s. It exhibits higher than 8.86 ENOB for input frequencies up to 78-MHz. The ADC consumes 0.85mW at a 1.1V supply and achieves a figure-of-merit of 51fJ/conversion-step.