Clocking Scheme Research Articles

A Charge-Domain Switched-Gm-C Band-Pass Filter Using Interleaved Semi-Passive Charge-Sharing Technique

A highly reconfigurable charge-domain switched- $g_{\mathrm {m}}$ -C biquad band-pass filter (BPF) topology that utilizes an interleaved semi-passive charge-sharing technique is proposed. It uses only switches, capacitors, linearity-enhanced $g_{\mathrm {m}}$ -stages and digital circuitry for a 3-phase non-overlapping clock scheme. Flexible tunability in both center frequency and −3dB bandwidth is achieved with a scaling-compatible implementation. A 4th-order BPF prototype operating at a 1.2GS/s sampling rate is designed with a cascade of two reconfigurable biquad stages in a 65nm LPE CMOS process. A tunable center frequency of 35–70MHz is measured with programmable bandwidths and a maximum stop-band rejection of 72dB. The measured in-band IIP3 is +12.5dBm. The filter prototype consumes 7.5mW total power from a 1.2V supply voltage, and occupies an active area of 0.17mm2.

The Mesochronous Dual-Clock FIFO Buffer

To increase system composability and facilitate timing closure, fully synchronous clocking is replaced by more relaxed clocking schemes, such as mesochronous clocking. Under this regime, the modules at the two ends of a mesochronous interface receive the same clock signal, thus operating under the same clock frequency, but the edges of the arriving clock signals may exhibit an unknown phase relationship. In such cases, clock synchronization is needed when sending data across modules. In this brief, we present a novel mesochronous dual-clock first-input–first-output (FIFO) buffer that can handle both clock synchronization and temporary data storage, by synchronizing data implicitly through the explicit synchronization of only the flow-control signals. The proposed design can operate correctly even when the transmitter and the receiver are separated by a long link whose delay cannot fit within the target operating frequency. In such scenarios, the proposed mesochronous FIFO can be extended to support multicycle link delays in a modular manner and with minimal modifications to the baseline architecture. When compared with the other state-of-the-art dual-clock mesochronous FIFO designs, the new architecture is demonstrated to yield a substantially lower cost implementation.

Improving the thermal stability of a CCD through clocking

Modern precise radial velocity spectrometers are designed to infer the existence of planets orbiting other stars by measuring few-nm shifts in the positions of stellar spectral lines recorded at high spectral resolution on a large-area digital detector. While the spectrometer may be highly stabilized in terms of temperature, the detector itself may undergo changes in temperature during readout that are an order of magnitude or more larger than the other optomechanical components within the instrument. These variations in detector temperature can translate directly into systematic measurement errors. We explore a technique for reducing the amplitude of CCD temperature variations by shuffling charge within a pixel in the parallel direction during integration. We find that this “dither clocking” mode greatly reduces temperature variations in the CCDs being tested for the NEID spectrometer. We investigate several potential negative effects this clocking scheme could have on the underlying spectral data.

Stateful Three-Input Logic with Memristive Switches

Memristive switches are able to act as both storage and computing elements, which make them an excellent candidate for beyond-CMOS computing. In this paper, multi-input memristive switch logic is proposed, which enables the function X OR (Y NOR Z) to be performed in a single-step with three memristive switches. This ORNOR logic gate increases the capabilities of memristive switches, improving the overall system efficiency of a memristive switch-based computing architecture. Additionally, a computing system architecture and clocking scheme are proposed to further utilize memristive switching for computation. The system architecture is based on a design where multiple computational function blocks are interconnected and controlled by a master clock that synchronizes system data processing and transfer. The clocking steps to perform a full adder with the ORNOR gate are presented along with simulation results using a physics-based model. The full adder function block is integrated into the system architecture to realize a 64-bit full adder, which is also demonstrated through simulation.

Maturing electron multiplying charge coupled device photon-counting with variable multiplication gain imaging for a coronagraphic instrument.

This is an introduction to a US government program that conducted high-contrast imaging experiments with an electron multiplying charge coupled device (EMCCD) in an interferometric coronagraph. This report will introduce the concepts of "charge blooming" and "starlight saturation" in the context of high-contrast astronomical imaging. These phenomena adversely effect the performance of high-contrast photon-counting instruments that do not use a mask to physically block starlight in the science channel of the coronagraph. The problems will be presented with the help of images taken with a commercial EMCCD camera in the visible nulling coronagraph at the Goddard Space Flight Center. A new clocking scheme for EMCCDs-variable multiplication gain clocking-will be proposed as a means for suppressing horizontal blooming and starlight saturation in an astronomical camera. This opening report will conclude with a discussion of design considerations for a new controller for high-contrast photon-counting with an EMCCD in a coronagraphic instrument. This controller will allow a single frame from an EMCCD to be scanned in multiple modes-photon-counting and digitization-with a variable multiplication gain clock to enable direct imaging of an exoplanet and wavefront control of a coronagraph, simultaneously.

Adaptive Coherent Receiver Settings for Optimum Channel Spacing in Gridless Optical Networks

In this paper, we propose a novel circuit and system to optimize the spacing between optical channels in gridless (also called flexible-grid or elastic) networking. The method will exploit the beginning-of-life link margin by enabling the channel to operate in super-Nyquist dense wavelength division multiplexing mode. We present the work in the context of software-defined networking and high-speed optical flexible-rate transponders. The clock recovery scheme allows the mitigation of jitter by decoupling the contribution of high-jitter noise sources from the clock recovery loop. The method and associated algorithm are experimentally verified where a spectrum gain of up to 2 GHz in spacing between two channels in the Media Channel (MC) is obtained compared to conventional clocking strategies. We showed that the improvement is equivalent to increasing throughput, in a data-center interconnect scenario, by up to 300 giga-bits per second per route.

Low-latency adiabatic superconductor logic using delay-line clocking

Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic family. The switching energy of an AQFP gate can be arbitrarily reduced via adiabatic switching. However, AQFP logic has somewhat long latency due to the multiphase clocking scheme, in which each logic operation requires a quarter clock cycle. The latency in AQFP logic should be improved in order to design complex digital circuits such as microprocessors. In the present paper, we propose a low-latency clocking scheme for AQFP logic, which we call delay-line clocking. In delay-line clocking, the latency for each logic operation is determined by the propagation delay of the excitation current, which can be much shorter than a quarter clock cycle. Our numerical simulation shows that AQFP gates can operate with a latency of only a few picoseconds. We fabricated an AQFP circuit adopting delay-line clocking using the 10 kA/cm2 Nb high-speed standard process provided by the National Institute of Advanced Industrial Science and Technology. The circuit was demonstrated at 4 GHz with a latency of 10 ps per gate. The above results indicate that delay-line clocking can significantly reduce the latency in AQFP logic.

A Feedback-Friendly Large-Scale Clocking Scheme for Adiabatic Quantum-Flux-Parametron Logic Datapaths

Adiabatic quantum-flux-parametron (AQFP) is an energy-efficient superconductor logic family. Since AQFP gates are powered and clocked by ac excitation current, it is difficult to make feedback loops in datapaths at high clock frequencies, which should be solved in order to design large-scale digital circuits such as microprocessors. In this paper, we propose a novel clocking scheme, which we designate as hybrid clocking, to make feedback loops in AQFP datapaths at high clock frequencies. In hybrid clocking, an entire datapath is divided into two parts: the concurrent-flow block and the counter-flow block. In this way, clock skews are avoided, so that feedback closure can be made independent of clock frequencies. We conduct the simulation of an AQFP buffer chain adopting hybrid clocking at 5 GHz to demonstrate that feedback can be made at high clock frequencies. Then, we investigate the maximum allowable clock skew between AQFP gates using this approach, which is important for physical layout design. We find that, with some modifications to the amplitude of excitation current, the maximum allowable clock skew of 47 ps is achieved at 5 GHz. This large allowable clock skew ensures that hybrid clocking can be adopted in large-scale AQFP datapaths.

Fast, Ring-Based Design of 3-D Stacked DRAM

As computer memory increases in size and processors continue to get faster, the memory subsystem becomes a bottleneck to system performance. To mitigate the relatively slow dynamic random access memory (DRAM) chip speeds, a new generation of 3-D stacked DRAM is being developed, with lower power consumption and higher bandwidth. This paper proposes the use of 3-D ring-based data fabrics for fast data transfer between the chips in the 3-D stacked DRAM. The ring-based data fabric uses a fast standing wave oscillator to clock its transactions. With a fast clocking scheme and multiple channels sharing the same bus, more channels are utilized while significantly reducing the number of through-silicon vias. Our memory architecture using a ring-based scheme (MARS) can effectively trade off power, throughput, and latency to improve the system performance for different application spaces. Experimental results show that our ring-based data fabric can reduce read latencies and power consumption. MARS variants can deliver better latency (up to $\sim 4\times $ ), power (up to $\sim 8\times $ ), and performance per watt (up to $\sim 8\times $ ) over high bandwidth memory. We also compare our approach with Wide I/O, which is designed for power-constrained systems. MARS variants provide better latency (up to $\sim 8\times $ ) with similar performance per watt.

Robust optical clock transitions in trapped ions using dynamical decoupling

We present a novel method for engineering an optical clock transition that is robust against external field fluctuations and is able to overcome limits resulting from field inhomogeneities. The technique is based on the application of continuous driving fields to form a pair of dressed states essentially free of all relevant shifts. Specifically, the clock transition is robust to magnetic field shifts, quadrupole and other tensor shifts, and amplitude fluctuations of the driving fields. The scheme is applicable to either a single ion or an ensemble of ions, and is relevant for several types of ions, such as , , and . Taking a spherically symmetric Coulomb crystal formed by 400 ions as an example, we show through numerical simulations that the inhomogeneous linewidth of tens of Hertz in such a crystal together with linear Zeeman shifts of order 10 MHz are reduced to form a linewidth of around 1 Hz. We estimate a two-order-of-magnitude reduction in averaging time compared to state-of-the art single ion frequency references, assuming a probe laser fractional instability of . Furthermore, a statistical uncertainty reaching 2.9 × 10−16 in 1 s is estimated for a cascaded clock scheme in which the dynamically decoupled Coulomb crystal clock stabilizes the interrogation laser for an clock.

Globally Asynchronous, Locally Synchronous Clocking and Shared Interconnect for Large-Scale SFQ Systems

A globally asynchronous, locally synchronous clocking scheme for large-scale single flux quantum (SFQ) systems is proposed. In this scheme, the width of each data bus is extended to carry the corresponding clock signal. This signal activates the distribution of the clock signals within the receiving block. Based on this approach for intra-chip interconnect within SFQ systems, a configurable shared bus is also proposed. The data are attached to a tag, and a resulting data packet is sent to the shared bus. This packet is received by each block, but only processed if the tag matches the block identifier. By avoiding expensive comparators and multiplexers, the overhead of the global bus connection is reduced. The proposed approaches exploit the pulse-based nature and ambiguity of clock and data in SFQ technology – the data packet propagating through the interconnect carries a local clock signal.

A 16-nm Always-On DNN Processor With Adaptive Clocking and Multi-Cycle Banked SRAMs

Always-on subsystems in mobile/Internet of Things (IoT) SoCs process a variety of real-time sensor data deep neural network (DNN) classification workloads in a heavily constrained energy budget. This can be achieved with robust, low-voltage circuits, and specialized hardware accelerators. We present a 16-nm always-on DNN processor, which consists primarily of a microcontroller and a DNN accelerator with on-chip SRAM for the model weights. The design operates robustly from 0.4 to 1-V, with calibration-free automatic voltage/frequency tuning provided by tracking small non-zero razor timing error rates. A novel timing error-driven synchronization-free adaptive clocking scheme significantly reduces the adaptation latency to provide resilience to fast on-chip supply noise and reduce margins. To accommodate the tight energy constraints of always-on IoT workloads, we implement a multi-cycle SRAM read scheme that allows the memory voltage to scale at iso-throughput, improving energy efficiency across the entire operating range. The wide operating range allows for high performance at 1.36 GHz, low-power consumption downs to 750 μW, and stateof-the-art raw efficiency at 16-bit precision of 750 GOPS/W dense or 1.81 TOPS/W sparse.

Numerical investigationof clocking effect of impellerson a multistage pump

Purpose The purpose of this paper is to investigate the clocking effect of impellers and the superposition between pump stages caused by clocking effect in a five-stage centrifugal pump. Then the best clocking scheme in terms of vibration is tried to be provided as well. Design/methodology/approach All curves of pressure fluctuation in different impeller stages can be divided into two groups for the difference of 1/16 T in time domain. The difference is mostly in vibration frequency and amplitude, little in pump head and efficiency. Findings All curves of pressure fluctuation in different impeller stages can be divided into two groups for the difference of 1/16 T in time domain. The difference is mostly in vibration frequency and amplitude, little in pump head and efficiency. Research limitations/implications This research involves eight different impeller clocking schemes. The results show that the clocking effect has little influence in pump head and efficiency, but the influence in pressure fluctuation is larger. Practical implications The paper provides guidance for the design of multistage pump for better vibration performance. Originality/value This research involves eight different impeller clocking schemes, the results show that the clocking effect has little influence in pump head and efficiency, but the influence in pressure fluctuation is larger. Then the best clocking scheme In terms of vibration is tried to be provided through analysis.

Synchronous Circuit Design With Beyond-CMOS Magnetoelectric Spin–Orbit Devices Toward 100-mV Logic

The supply voltage scaling has become increasingly challenging in the advanced CMOS technology due to the threshold voltage requirement for transistor OFF leakage, limiting the system energy efficiency. Spintronic logic utilizes the physical quantity of magnetization or spin as a computation variable, offering new design paradigms in terms of ultralow voltage operation and nonvolatility, but suffering from switching inefficiency of the charge-to-spin conversion. The magnetoelectric spin–orbit (MESO) device has been proposed as a new alternative logic device candidate to solve these issues by magnetoelectric transduction using a novel multiferroic oxide [both ferroelectric (FE) and antiferromagnetic], a ferromagnet and a spin injection layer. It enables a path toward 10–100 $\times $ switching energy reduction compared to CMOS inverter in 2018 node, due to the device and material innovations of a novel switching mechanism. In this paper, in order to build a MESO logic family for new circuit and architecture exploration, we propose for the first time the fundamental building blocks such as MESO sequential and combinatorial circuits for the synchronous logic operation. We employ a transistor sharing and a novel multiphase clocking scheme to address the circuit design issues such as clock control, directionality of state propagation, and power gating and enable the design exploration for MESO digital logic. Based on the proposed circuit techniques, we demonstrate these MESO logic functions operating at a supply voltage of 100 mV and a clock period of 1.2 ns with 320-ac FE polarization through the circuit simulations.

Experimental study of the application feasibility of a novel chip-scale atomic clock scheme.

We report on research into a microfabricated 87Rb vapor cell with differential detection. Elliptically polarized light is used to interact with alkali atoms to generate coherent population trapping (CPT) resonance, and the CPT signal is obtained by detecting the Faraday rotation effect with differential detection technology. To move closer to an actual chip-scale atomic clock (CSAC), we reduce the volume of the experimental apparatus and use a divergent laser beam to interact with the atoms. We obtain the short-term frequency stability of the CSAC based on the differential detection scheme and compare it with that of a conventional CSAC. The results show that the frequency stability is more than two times better than that of current commercial CSAC devices with the same power consumption and volume.

A GALS design based on multi-frequency clocking for digital switching noise reduction

In this paper, we investigate two design techniques to reduce the digital switching noise on the power supply lines: a multi-frequency clocking (MFC) and a globally asynchronous locally synchronous (GALS) design technique. By deploying an MFC design, we can spread the switching current peaks over a frequency band, which results in the supply noise reduction. With the use of a GALS technique, we partition a large synchronous design into some smaller locally synchronous modules (LSMs) which are clocked by their own local clocks. Each local clock signal can be different from the other in terms of frequency or phase. Thus, we can also distribute the digital switching activities inside circuits over time, which leads to the supply noise reductions. The experimental results on a commercial Field Programmable Gate Array (FPGA) Spartan-3 (XC3S400-TQ144) show that the noise reduction rates can be achieved up to 17.4 dB for a GALS system with 8 LSMs, and 19.2 dB for the joint use of the MFC and GALS techniques with 4 LSMs. Moreover, as a real design example, a DES crypto processor with the deployment of GALS design and multi-frequency clocking strategy is also implemented and evaluated. The noise reduction rate is achieved about 19.5 dB at the fundamental frequency.

Chip-Scale Molecular Clock

An ultra-stable time-keeping device is presented, which locks its output clock frequency to the rotational-mode transition of polar gaseous molecules. Based on a high-precision spectrometer in the sub-terahertz (THz) range, our new clocking scheme realizes not only fully electronic operation but also implementations using mainstream CMOS technology. Meanwhile, the small wavelength of probing wave and high absorption intensity of our adopted molecules (carbonyl sulfide, 16O12C32S) also enable miniaturization of the gas cell. All these result in an “atomic-clock-grade” frequency reference with small size, power, and cost. This paper provides the architectural and chip-design details of the first proof-of-concept molecular clock using a 65-nm CMOS bulk technology. Using a 231.061-GHz phase-locked loop (PLL) with frequency-shift keying (FSK) modulation and a sub-THz FET detector with integrated lock-in function, the chip probes the accurate transition frequency of carbonyl sulfide (OCS) gas inside a single-mode waveguide, and accordingly adjusts the 80-MHz output of a crystal oscillator. The clock consumes only 66 mW of dc power and has a measured Allan deviation of 3.8 $\times $ 10 $^{-10}$ at an averaging time of $\tau =1000$ s.

Controlling systematic frequency uncertainties at the 10−19 level in linear Coulomb crystals

Trapped ions are ideally suited for precision spectroscopy, as is evident from the remarkably low systematic uncertainties of single-ion clocks. The major weakness of these clocks is the long averaging time, necessitated by the low signal of a single atom. An increased number of ions can overcome this limitation and allow for the implementation of novel clock schemes. However, this presents the challenge to maintain the excellent control over systematic shifts of a single particle in spatially extended and strongly coupled many-body systems. We measure and deduce systematic frequency uncertainties related to spectroscopy with ion chains in a newly developed rf trap array designed for precision spectroscopy on simultaneously trapped ion ensembles. For the example of an In${}^+$ clock, sympathetically cooled with Yb${}^+$ ions, we show in our system that the expected systematic frequency uncertainties related to multi-ion operation can be below $1\times10^{-19}$. Our results pave the way to advanced spectroscopy schemes such as entangled clock spectroscopy and cascaded clock operation.

A charge pump system with new regulation and clocking scheme

A charge pump system with new regulation and clocking scheme

High Efficiency Cross-Coupled Charge Pump Circuit with Four-Clock Signals

A fully integrated cross-coupled charge pump circuit for boosting dc-to-dc converter applications with four-clock signals has been proposed. With the new clock scheme, this charge pump eliminates all of the reversion power loss and reduces the ripple voltage. In addition, the largest voltage differences between the terminals of all transistors do not exceed the power supply voltage for solving the gate-oxide overstress problem in the conventional charge pump circuits and enhancing the reliability. This proposed charge pump circuit does not require any extra level shifter; therefore, the power efficiency is increased. The proposed charge pump circuit has been simulated using Spectre in the TSMC 0.18 μm CMOS process. The simulation results show that the maximum voltage conversion efficiency of the new 3-stage cross-coupled circuit with an input voltage of 1.5Vis 99.8%. According to the comparison results of the conventional pump and the enhanced charge pump proposed, the output ripple voltage has been significantly reduced.