Abstract

A highly reconfigurable charge-domain switched- $g_{\mathrm {m}}$ -C biquad band-pass filter (BPF) topology that utilizes an interleaved semi-passive charge-sharing technique is proposed. It uses only switches, capacitors, linearity-enhanced $g_{\mathrm {m}}$ -stages and digital circuitry for a 3-phase non-overlapping clock scheme. Flexible tunability in both center frequency and −3dB bandwidth is achieved with a scaling-compatible implementation. A 4th-order BPF prototype operating at a 1.2GS/s sampling rate is designed with a cascade of two reconfigurable biquad stages in a 65nm LPE CMOS process. A tunable center frequency of 35–70MHz is measured with programmable bandwidths and a maximum stop-band rejection of 72dB. The measured in-band IIP3 is +12.5dBm. The filter prototype consumes 7.5mW total power from a 1.2V supply voltage, and occupies an active area of 0.17mm2.

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