Clock Signal Research Articles

ZEITLUPE Promotes ABA-Induced Stomatal Closure in Arabidopsis and Populus.

Plants balance water availability with gas exchange and photosynthesis by controlling stomatal aperture. This control is regulated in part by the circadian clock, but it remains unclear how signalling pathways of daily rhythms are integrated into stress responses. The serine/threonine protein kinase OPEN STOMATA 1 (OST1) contributes to the regulation of stomatal closure via activation of S-type anion channels. OST1 also mediates gene regulation in response to ABA/drought stress. We show that ZEITLUPE (ZTL), a blue light photoreceptor and clock component, also regulates ABA-induced stomatal closure in Arabidopsis thaliana, establishing a link between clock and ABA-signalling pathways. ZTL sustains expression of OST1 and ABA-signalling genes. Stomatal closure in response to ABA is reduced in ztl mutants, which maintain wider stomatal apertures and show higher rates of gas exchange and water loss than wild-type plants. Detached rosette leaf assays revealed a stronger water loss phenotype in ztl-3, ost1-3 double mutants, indicating that ZTL and OST1 contributed synergistically to the control of stomatal aperture. Experimental studies of Populus sp., revealed that ZTL regulated the circadian clock and stomata, indicating ZTL function was similar in these trees and Arabidopsis. PSEUDO-RESPONSE REGULATOR 5 (PRR5), a known target of ZTL, affects ABA-induced responses, including stomatal regulation. Like ZTL, PRR5 interacted physically with OST1 and contributed to the integration of ABA responses with circadian clock signalling. This suggests a novel mechanism whereby the PRR proteins—which are expressed from dawn to dusk—interact with OST1 to mediate ABA-dependent plant responses to reduce water loss in time of stress.

An Asynchronous Bundled-Data Barrel Shifter Design That Incorporates a Deterministic Completion Detection Technique

A design for an asynchronous bundled-data barrel shifter that incorporates a deterministic completion detection circuitry is proposed. A bundled-data asynchronous circuit is inherently free from challenges associated with clock signals, but it is devoid of information pertaining to propagation delay through the circuit. An obvious solution is to produce the acknowledge signal at least <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\delta $ </tex-math></inline-formula> delay units after the arrival of the request signal, where <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\delta $ </tex-math></inline-formula> is the maximum propagation delay through the circuit. However, similar to synchronous circuits, such bundle-data asynchronous approach does not take advantage of times where the propagation delay through the circuit is less than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\delta $ </tex-math></inline-formula> . This brief proposes a design for a deterministic completion detection scheme for an asynchronous bundled-data barrel shifter. Once the request signal is active, the shifting operation begins, and the acknowledge signal is generated after a delay that matches the actual shifting delay associated with the shift amount using a deterministic completion detection scheme. The shifter can reduce the idle time between the time its output is ready and the start of the next shift cycle by using a deterministic completion detection circuit. In this brief, the proposed design of the asynchronous barrel shifter and its average delay is analyzed. Its performance is also compared against its synchronous counterpart.

Design of True Random Number Generator Based on Multi-Stage Feedback Ring Oscillator

True random number generators (TRNGs) play an important role in encryption systems. In this brief, a novel method of generating true random numbers on a field-programmable gate array (FPGA) is proposed based on the random jitter of a multi-stage feedback ring oscillator (MSFRO) as the entropy source. Based on the traditional ring oscillator, a multi-stage feedback structure is added to enlarge the range of clock jitter, and improve the frequency of clock sampling and the randomness of the entropy source. Different from the traditional clock sampling structure, we use the clock jitter signal generated by the MSFRO to sample the clock signal generated by the phase-locked loop (PLL) of the FPGA. The obtained output value is operated by XOR to reduce the deviation of the output value and improve its randomness. The TRNG is implemented in Xilinx Virtex-6 FPGA, which has low hardware resource consumption and high throughput. The entropy source classification, hardware resources and throughput are compared with those of existing TRNGs. The results showed that the proposed TRNG only consumed 24 LUTs and 2 DFFs. Compared with other TRNGs, this design has very low hardware resource consumption and its throughput is up to 290 Mbps. The random bit sequence generated by this TRNG passes the NIST SP800-22 test and the NIST SP800-90B test.

Circadian Regulation of Retinal Pigment Epithelium Function.

The retinal pigment epithelium (RPE) is a single layer of cells located between the choriocapillaris vessels and the light-sensitive photoreceptors in the outer retina. The RPE performs physiological processes necessary for the maintenance and support of photoreceptors and visual function. Among the many functions performed by the RPE, the timing of the peak in phagocytic activity by the RPE of the photoreceptor outer segments that occurs 1–2 h. after the onset of light has captured the interest of many investigators and has thus been intensively studied. Several studies have shown that this burst in phagocytic activity by the RPE is under circadian control and is present in nocturnal and diurnal species and rod and cone photoreceptors. Previous investigations have demonstrated that a functional circadian clock exists within multiple retinal cell types and RPE cells. However, the anatomical location of the circadian controlling this activity is not clear. Experimental evidence indicates that the circadian clock, melatonin, dopamine, and integrin signaling play a key role in controlling this rhythm. A series of very recent studies report that the circadian clock in the RPE controls the daily peak in phagocytic activity. However, the loss of the burst in phagocytic activity after light onset does not result in photoreceptor or RPE deterioration during aging. In the current review, we summarized the current knowledge on the mechanism controlling this phenomenon and the physiological role of this peak.

10-Bit 5 MS/s Successive Approximation Register Analog-to-Digital Converter with a Phase-Locked Loop and Modified Bootstrapped Switch for a BLDC Motor Drive

In this paper, we present a successive approximation register (SAR) analog-to-digital converter (ADC) with a charge-pump (CP) phase-locked loop (PLL) and a bootstrapped switch, also called PLL-SAR ADC. To meet system-on-chip (SOC) and industrial requirements, the proposed SAR ADC and the control circuits of electric vehicles must be integrated into a single chip and be fabricated using the TSMC 0.25-μm 1P3M complementary metal oxide semiconductor (CMOS) high-voltage process. It is difficult to implement a high-speed SAR ADC with the TSMC 0.25-μm CMOS high-voltage process because it includes an N-type buried layer, which shorts all p-type metal oxide semiconductor field-effect transistor (PMOSFET) bodies together to withstand high voltages. In the proposed PLL-SAR ADC, two clock signals, an external clock signal and an internal clock signal from the CP-PLL, are provided to guarantee that a correct clock signal is fed. This design improves the robustness of the designed system. A monotonic capacitor-switching procedure is considered to reduce power consumption. Furthermore, a bootstrapped switch was added along with a dummy switch and a dummy transistor to eliminate disturbances in the input voltages and to improve the device’s anti-noise capability. Moreover, a two-stage dynamic comparator was used to prevent kickback noise induced by the parasitic capacitors. The measurements indicate that the signal-to-noise-and-distortion ratio, effective number of bits, power consumption, and chip area are 53.82 dB, 8.65 bits, 1.256 mW, and 1.261 × 0.975 mm2, respectively. The FoM is approximately 0.625 pJ/conv-step at 1.256 mW, 8.65 bits, and 5 MS/s. The high sampling rate of 5 MS/s and high accuracy of 8.65 bits are the main advantages of the proposed PLL-SAR ADC.

Precise determination of characteristic laser frequencies by an Er-doped fiber optical frequency comb

Femtosecond optical frequency combs correlate the microwave and optical frequencies accurately and coherently. Therefore, any optical frequency in visible to near-infrared region can be directly traced to a microwave frequency. As a result, the length unit “meter” is directly related to the time unit “second”. This paper validates the capability of the national wavelength standards based on a home-made Er-doped fiber femtosecond optical frequency comb to measure the laser frequencies ranging from visible to near-infrared region. Optical frequency conversion in the femtosecond optical frequency comb is achieved by combining spectral broadening in a highly nonlinear fiber with a single-point frequency-doubling scheme. The signal-to-noise ratio of the beat notes between the femtosecond optical frequency comb and the lasers at 633, 698, 729, 780, 1064, and 1542 nm is better than 30 dB. The frequency instability of the above lasers is evaluated by using a hydrogen clock signal with a instability of better than 1 × 10−13 at 1-s averaging time. The measurement is further validated by measuring the absolute optical frequency of an iodine-stabilized 532-nm laser and an acetylene-stabilized 1542-nm laser. The results are within the uncertainty range of the international recommended values. Our results demonstrate the accurate optical frequency measurement of lasers at different frequencies using the femtosecond optical frequency comb, which is not only important for the precise and accurate traceability and calibration of the laser frequencies, but also provides technical support for establishing the national wavelength standards based on the femtosecond optical frequency comb.

Simulated Hough Transform Model Optimized for Straight-Line Recognition Using Frontier FPGA Devices

The use of the Hough transforms to identify shapes or images has been extensively studied in the past using software for artificial intelligence applications. In this article, we present a generalization of the goal of shape recognition using the Hough transform, applied to a broader range of real problems. A software simulator was developed to generate input patterns (straight-lines) and test the ability of a generic low-latency system to identify these lines: first in a clean environment with no other inputs and then looking for the same lines as ambient background noise increases. In particular, the paper presents a study to optimize the implementation of the Hough transform algorithm in programmable digital devices, such as FPGAs. We investigated the ability of the Hough transform to discriminate straight-lines within a vast bundle of random lines, emulating a noisy environment. In more detail, the study follows an extensive investigation we recently conducted to recognize tracks of ionizing particles in high-energy physics. In this field, the lines can represent the trajectories of particles that must be immediately recognized as they are created in a particle detector. The main advantage of using FPGAs over any other component is their speed and low latency to investigate pattern recognition problems in a noisy environment. In fact, FPGAs guarantee a latency that increases linearly with the incoming data, while other solutions increase latency times more quickly. Furthermore, HT inherently adapts to incomplete input data sets, especially if resolutions are limited. Hence, an FPGA system that implements HT is inefficient for small sets of input data but becomes more cost-effective as the size of the input data increases. The document first presents an example that uses a large Accumulator consisting of 1100 × 600 Bins and several sets of input data to validate the Hough transform algorithm as random noise increases to 80% of input data. Then, a more specifically dedicated input set was chosen to emulate a real situation where a Xilinx UltraScale+ was to be used as the final target device. Thus, we have reduced the Accumulator to 280 × 280 Bins using a clock signal at 250 MHz and a few tens input points. Under these conditions, the behavior of the firmware matched the software simulations, confirming the feasibility of the HT implementation on FPGA.

A 6.15–10.9 Gb/s 0.58 pJ/Bit Reference-Less Half-Rate Clock and Data Recovery With “Phase Reset” Scheme

This paper presents a low power injection-locked oscillator (ILO)-type clock and data recovery (CDR) in 40 nm CMOS. An efficient ``phase reset'' scheme is proposed to periodically realign the clock phase to the rising edge of data. The frequency information is extracted by comparing the rising edge of the data and the clock after aligning the phase using a bang-bang phase detector (BBPD). Additionally, a low power injection-locked two-stage ring digitally controlled oscillator (ILDCO) is employed to provide four-phase quadrature clock and significantly reduce the power consumption. Based on the proposed architecture, the fabricated CDR consumes only 5.8 mW from a 0.9 V supply, while being able to extract the clock signal from 6.15 to 10.9 Gb/s input data with a measured jitter tolerance (JTOL) of 0.15 UIpp at the highest frequency, indicating that the CDR meets the OC-192 mask. Furthermore, the proposed CDR demonstrates a substantial improvement in the power efficiency of 0.58 pJ/bit.

Ultra-Low Power, Emission Gate Driver With Pulse Width Modulation Using Low-Temperature Poly-Si Oxide Thin-Film Transistors

We report a novel emission gate driver using low- temperature poly-Si oxide (LTPO) thin-film transistors (TFTs). The proposed circuit consists of eight p-type low-temperature poly-Si (LTPS) and four n-type amorphous InGaZnO (a-IGZO) TFTs. The output pulse width is adjustable by changing the position of starting control signal which has constant pulse width without additional clock signals. The emission gate driver releases the output signals with various duty ratios. Excellent gate driving performance is achieved from the LTPO emission gate driver, although the a-IGZO TFTs have the threshold voltage of −5.5 V. In addition, the power consumption is as low as 5.98 mW in case of 80 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {\mu }\text{s}$ </tex-math></inline-formula> pulse, 10 times of gate pulse, at refresh rate of 120 Hz with full high-definition ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1920\times1080$ </tex-math></inline-formula> ) for active-matrix organic light- emitting diode (AMOLED) display.

Nonlinear correction of a laser scanning interference system based on a fiber ring resonator.

The laser scanning interferometry system has been successfully applied to many measurement fields because of its efficient measurement ability. However, the practical application ability of this measurement method is restricted due to the laser tuning nonlinearity. In this paper, the fiber ring resonator is equidistant in the frequency domain, which is used as the external clock signal to resample the main interference signal so as to realize the equifrequency sampling of the laser scanning interference system and correct the tuning nonlinearity. The final experimental result shows that this method can effectively reduce the phase noise caused by tuning nonlinearity and improve the performance of the system.

Design, implementation, and qualification of high-performance time and frequency reference for the MeerKAT telescope

The details of the MeerKAT radio telescope’s time and frequency reference subsystem that enables sampling via low-jitter, low-drift microwave clock signals, and absolute timing (≤5 ns accurate) are discussed. The subsystem’s microwave and pulse per second transmission parts are now fully qualified and commissioned for the ultra high frequency (UHF) and L-bands and also provide for a 100-MHz interface and timing interfaces for S-band receivers that were installed. The subsystem includes a cable measurement system called the Karoo array timing system (KATS). Performance and differences on different bands and seasonal drift of the cable delay measurement of KATS are reported. A time scale called the Karoo Telescope Time (KTT) (which is estimated from tracking a few atomic clocks via new software) and the issuing of timing bulletins to users have been largely implemented and verified. Absolute timing calibration and linkage of KTT to the global positioning system time scale and to different UTC(k) realizations of the Coordinated Universal Time (UTC) instances are described. The subsystem uniquely enables high-fidelity sampling and stable tied array configuration. The latter configuration enables timing and transient science over time spans of 5 to 10 years. Simultaneous subarraying is supported. The backend is unique for radio telescopes in terms of being very deterministic as far as timing is concerned.

A New Perspective of Flexible Clocking Ideology for Driving and Devising Circuits in Emerging Resource-Constrained Applications

Clock is the most important signal in electronic system. In current practice, the dominant clocking style is the fixed-frequency approach. For a given application, the clock signal is only required to work at a few selected frequencies. Moreover, in the process of performing a task, it must not change its frequency. This style has worked well in the past. However, it is preventing information processing efficiency from being raised to next level. Worse yet, the emergence of resource-constrained applications, such as edge computing and IoT, can render this approach unserviceable. In this paper, a new perspective of flexible clocking ideology is advocated. It promotes the use of a clock generator, TAF-DPS, that possesses features of “arbitrary frequency generation” and “instantaneous frequency switching”. Owing to its superior capability in synthesizing waveform, TAF-DPS can handle many signal processing problems in a more elegant manner and serve some special purposes more efficiently. Further, it can be used for generating data for security purposes. TAF-DPS is especially valuable for environments with large frequency instability, which is a major problem in resource-constrained applications. The contribution of this paper is the advocacy of a new perspective of flexible clocking. This ideology is gradually developed in this paper as the argument is carried out through examples of novel architectures enabled by TAF-DPS. The perspective naturally emerges from the collective effect of those novel architectures. The large number of emerging applications, exemplified by edge computing and IoT, inspire system-level innovations that inevitably present new challenges to circuit-level. Those challenges are so demanding that they require overhaul in our circuit design philosophy. This new perspective is such an overhaul in fundamental level. Its aim is to answer the challenges, for better serving the emerging demands in higher levels.

A 18.7 TOPS/W Mixed-Signal Spiking Neural Network Processor With 8-bit Synaptic Weight On-Chip Learning That Operates in the Continuous-Time Domain

We present a mixed-signal spiking neural networks processor with 8-bit synaptic weight on-chip learning in 40 nm CMOS that consists of a 10k mixed-signal synapse circuit and 100 analog leaky integrate-and-fire (LIF) neuron circuits. The processor has no clock signal except in peripheral circuits for I/O, and neuron and synapse circuits can operate asynchronously in the continuous-time domain, just like biological neurons. We demonstrate the energy efficiency of 6.24–18.7 TOPS/W in a multitarget spike learning task.

A-Si TFT Integrated Gate Driver Workable at −40°C Using Bootstrapped Carry Signal

A thin-film transistors (TFTs) integrated gate driver which can work well at low temperature down to -40 °C is proposed and demonstrated. The carry signal (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</sub> ) of the driver, being generated through the voltage bootstrapping approach using a C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</sub> -connected capacitor, is used to pre-charge the following stage of the driver. As the rising and falling time of C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</sub> is much shorter than that of the gate driving signal G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</sub> , the bootstrapping voltage is increased and voltage loss of the pre-charge transistor can be much reduced, to avoid the driver’s malfunction at low temperature. This structure further benefits maintaining the driving speed over long operation time at high temperature. On the other hand, the G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</sub> , instead of C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</sub> , is used to reset the gate driver to suppress the voltage feed-through effects. One single stage of the driver consists of 11 TFTs and 2 capacitors, driven by 4 clock signals with the duty ratio of 25%. An a-Si:H TFTs implemented single stage circuit of the driver occupies an area of 250 μm×1099 μm. Measurements show that the output voltage magnitude can be maintained well when temperature varies from -40 °C to 80 °C. Moreover, the rising-time and falling-time increase of the output pulse are both less than 3 μs after 240 hours of the accelerated high temperature aging operations.

Architectures and Synchronization Techniques for Distributed Satellite Systems: A Survey

Cohesive Distributed Satellite Systems (CDSSs) is a key enabling technology for the future of remote sensing and communication missions. However, they have to meet strict synchronization requirements before their use is generalized. When clock or local oscillator signals are generated locally at each of the distributed nodes, achieving exact synchronization in absolute phase, frequency, and time is a complex problem. In addition, satellite systems have significant resource constraints, especially for small satellites, which are envisioned to be part of the future CDSSs. Thus, the development of precise, robust, and resource-efficient synchronization techniques is essential for the advancement of future CDSSs. In this context, this survey aims to summarize and categorize the most relevant results on synchronization techniques for Distributed Satellite Systems (DSSs). First, some important architecture and system concepts are defined. Then, the synchronization methods reported in the literature are reviewed and categorized. This article also provides an extensive list of applications and examples of synchronization techniques for DSSs in addition to the most significant advances in other operations closely related to synchronization, such as inter-satellite ranging and relative position. The survey also provides a discussion on emerging data-driven synchronization techniques based on Machine Learning (ML). Finally, a compilation of current research activities and potential research topics is proposed, identifying problems and open challenges that can be useful for researchers in the field.

Circadian Clock, Glucocorticoids and NF-κB Signaling in Neuroinflammation- Implicating Glucocorticoid Induced Leucine Zipper as a Molecular Link

Inflammation including neuroinflammation is considered a protective response and is directed to repair, regenerate, and restore damaged tissues in the central nervous system. Persistent inflammation due to chronic stress, age related accrual of free radicals, subclinical infections or other factors lead to reduced survival and increased neuronal death. Circadian abnormalities secondary to altered sleep/wake cycles is one of the earliest signs of neurodegenerative diseases. Brain specific or global deficiency of core circadian trans-activator brain and muscle ARNT (Arylhydrocarbon Receptor Nuclear Translocator)-like protein 1 (BMAL1) or that of the transrepressor REV-ERBα, impaired neural function and cognitive performance in rodents. Consistently, transcripts of inflammatory cytokines and host immune responses have been shown to exhibit diurnal variation, in parallel with the disruption of the circadian rhythm. Glucocorticoids that exhibit both a circadian rhythm similar to that of the core clock transactivator BMAL1 and tissue specific ultradian rhythm are critical in the control of neuroinflammation and re-establishment of homeostasis. It is widely accepted that the glucocorticoids suppress nuclear factor-kappa B (NF-κB) mediated transactivation and suppress inflammation. Recent mechanistic elucidations suggest that the core clock components also modulate NF-κB mediated transactivation in the brain and peripheral tissues. In this review we discuss evidence for interactions between the circadian clock components, glucocorticoids and NF-κB signaling responses in the brain and propose glucocorticoid induced leucine zipper (GILZ) encoded by Tsc22d3, as a molecular link that connect all three pathways in the maintenance of CNS homeostasis as well as in the pathogenesis of neuroinflammation-neurodegeneration.

Area and Energy Efficient QCA Based Compact Serial Concatenated Convolutional Code Encoder

Quantum-dot Cellular Automata (QCA) is a transistor-less technology known for its low power consumption and higher clock rate. Serial Concatenated Convolutional Coding (SCCC) encoder is a class of forward error correction. This paper picturizes the implementation of the outer encoder as a (7, 4, 1) Bose Chaudhary Hocquenghem encoder that serves the purpose of burst error correction, a pseudo-random inter-leaver used for permuting of systematic code words and finally the inner encoder which is used for the correction of random errors in QCA. Two different architectures of the SCCC encoder have been proposed and discussed in this study. In the proposed two architectures, the first based on external clock signals whereas the second based on internal clock generation. The sub-blocks outer encoder, pseudo-random inter-leaver and inner encoder of the SCCC encoder are optimized, implemented and simulated using QCADesigner and then integrated to design a compact SCCC encoder. The energy dissipation is computed using QCADesigner-E. The proposed SCCC encoder reduced the total area by 46% and energy dissipation by 50% when compared to the reference SCCC encoder. The proposed encoders are more efficient in terms of cell count, energy dissipation and area occupancy respectively.

A Novel Time-to-Amplitude Converter and a Low-Cost Wide Dynamic Range FPGA TDC for LiDAR Application

This paper demonstrates a low-cost wide dynamic range FPGA time-to-digital converter (TDC) and a time-to-amplitude converter (TAC) based on an embedded XOR gate of the FPGA and a low-complexity circuitry. TACs and TDCs are important for distance measurements in LiDAR systems in a wide range of applications from self-driving cars to topographic mapping. LiDAR&#x2019;s high cost, relatively large size and complexity are important implementation challenges that need to be addressed. In the literature, external circuits are used to provide low phase noise clock signals into the FPGA TDC to measure long range time intervals adding to the complexity and cost. Our TDC can measure a wide dynamic range of 1 ms with high precision using a low-cost FPGA board. Calibration using dynamic phase-shifting (DPS) is conducted with a resolution of 18 ps. The performance measurements gave us insight on the relative temperature insensitive regions for operating the TDC. The ideal range was found to be 24&#x00B0;C to 39&#x00B0;C. We also present a novel TAC design to demonstrate that one XOR gate of a low-cost Artix-7 FPGA and a simple low-cost circuitry can detect a phase difference as low as 18 ps. The TAC&#x2019;s linearity is presented through INL and DNL test results. For every additional channel, our TAC requires only one XOR gate in the FPGA chip and a low complexity circuitry. This allows for multichannel operation and larger area availability for use in other implementations. Performance measurements show our TAC to be highly insensitive to temperature and voltage changes.

Radarski sistem za praćenje ciljeva velikih brzina zasnovan na upotrebi BPSK signala i digitalnoj kompenzaciji doplerovog pomaka

Introduction/purpose: This paper presents a model of a high speed target radar tracking system that is much simpler than the existing ones. The Doppler shift is compensated before signal compression, simultaneously with the modification of the clock signal in the compression filter. This is possible thanks to the development of FPGA technology. The most important for this application are very fast clock control units which enable operation with different frequency references up to 1 GHz with an accuracy far below 1 Hz. Methods: In this paper, the methodology of mathematical modeling and simulation is used. Results: The results of the analysis of the most important effects in radars caused by high-speed targets are presented and discussed - target migration through resolution cells and compression filter response distortion due to high target acceleration. Conclusion: Thanks to flexible RF and signal processing hardware, complex radar processing procedures are not required. The sensitivity of the BPSK signal to the Doppler shift (which is usually considered a disadvantage) can be used to reject targets at a slightly different rate. This system can be used in space debris tracking, airspace target tracking, car driving, etc.

DEVELOPMENT OF OFFICIAL INDONESIA STANDARD TIME : TEMPERATURE CONTROL SYSTEM FOR CAESIUM ATOMIC CLOCK

Every country should have an official time standard which called local coordinated universal time, UTC(k). Badan Standardisasi Nasional (BSN) has developed an official standard time, namely UTC(IDN) which is used as Indonesia Standard Time. The UTC(IDN) contributes to calculation of coordinated universal time (UTC). In order to generate the UTC(IDN), the output of 1 pulse per second signal of caesium atomic clock is utilized as the actual signals of this standard. A distribution amplifier is used to distribute the signal. Combination of time transfer system (TTS-3) and GPS are employed for comparison of UTC and UTC(IDN). TTS-3 automatically calculated the difference and it is steered by using certain algorithm. Time synchronization to the standard can be conducted through network time protocol (NTP) server, i.e., ntp.bsn.go.id. The time can be automatically synchronized using internet time or certain program at each computer or machine. The results of this work show that the time differences between UTC – UTC(IDN) vary from 43.2 ns to 1729.9 ns. UTC(IDN) has frequency and time stability of 3.6 x 10 -14 Hz/Hz per 5 days and 3.1 ns per 5 days, respectively which are in good agreement to the international time reference. A shielding chamber with temperature control system has been built to keep the ambient temperature of caesium atomic clock at (23 ± 1) ᵒC. It can be concluded that BSN has been developing and disseminating the UTC(IDN) as an Indonesia Standard Time that can support the regulation of time synchronization in Indonesia. A new temperature control system is proposed to stabilize the ambient temperature of caesium atomic clock. The temperature control system supports an accurate and stable UTC(IDN).