Clock Signal Research Articles

P‐1.7: Novel Design of Boost Circuit in Pixel

This paper presented a new design of boost circuit in pixel, which could meet the demand for high driving voltage in some special applications and avoid the increasing cost caused by using chips with high‐voltage output. The main circuit of pixel unit contained 3 TFTs and 3 capacitors. Compared with conventional TFT‐LCD, 2 new kinds of signals were added. 1 clock signal was shared by all pixels and 1 additional scanning signal was designed for each row. Through reasonable circuit parameters and timing design, the circuit scheme proposed in this paper could achieve effective boost. The simulation showed the pixel voltage was increased by 60%, compared with the voltage provided by the data line. In the actual sample verification, the voltage was increased by 50%. Therefore, the feasibility of circuit function was verified. Details of design, simulation and verification would be introduced in the text.

Design and Integrate Real Time Clock and Temperature Digital Signal Processing with ARM System

The integrated circuit had been developed rapidly from microprocessor to microcontroller and System-on-Chip (SoC) just happen within a few decade. The development is continuing as the demand for the functionality increase. The Real Time Clock (RTC) is one of the peripherals most widely used inside the microcontroller. Besides, when Moore’s law is still applied, the number of transistor will increase, so does the temperature. Thus, the temperature digital signal processing (TDSP) unit had become an important peripheral to monitor the system-on-chip temperature. In this paper, these two Intellectual Property which are RTC and TDSP are designed and integrated into ARM system. The system architecture and implementation strategies are discussed. The results were run and simulated in the Synopsys software.

P‐1.9: The Effect of Lateral Capacitance on Flat‐Panel Display with Gate Driver Circuits Integrated in Active Area

A highly integrated display panel, in which gate driving circuit was totally integrated in active area, was designed and lit up. The issue of this panel, caused by lateral capacitance between clock signal line and source line, was studied systemically. The results provide reference for the development of higher integrated and more intelligent panel in the future.

A distributed control for accurate active‐power sharing in islanded microgrids subject to clock drifts

Inverters-based islanded microgrids are operated by local digital signal processors, driven by their own local clocks. These local clocks have drifts affecting the clock signals which are used to control the inverters in real time. In this scenario, a steady-state deviation is observed in active power sharing, degrading the microgrid performance. This paper presents a new control scheme that improves the microgrid performance by cancelling the active power sharing error due to clock drifts. The study includes a theoretical stability analysis and a design procedure of the control parameters based on the dynamic characteristics. Finally, selected experimental results are obtained in a laboratory microgrid with four inverters. In this setup, each inverter was equipped with its digital signal processor with drifting local clock.

Gated Clock and Revised Keeper (GCRK) Domino Logic Design in 16 nm CMOS Technology

ABSTRACT This paper proposed a domino logic namely “Gated Clock and Revised Keeper (GCRK)” domino logic 16 nm CMOS technology. The proposed domino logic has a revised keeper circuitry to reduce the power consumption in the circuit. A multiplexer is added in the GCRK design for gating the clock signal during sleep mode while maintaining the state of the domino logic. Total power consumption, delay and power-delay-product (PDP) of 16-bit OR gate GCRK domino logic and existing domino logic designs are calculated and compared. The existing domino logic techniques considered in this paper are – Leakage tolerant multiphase keeper domino logic (LTMK), high-speed domino logic (HSD), clock delayed sleep mode domino logic (CDSMD), grounded pmos keeper domino logic (GPKD) and foot driven stack transistor domino logic (FDSTDL). The proposed design shows significant improvement in PDP with respect to the existing designs. The PDP of proposed design (LTMK) is improved to 99.98%, 88.75%, 11.54% and 37.11% as compared to LTMK, HSD, GPDK and FDSTDL designs, respectively. Noise analysis and Monte Carlo simulation show that the proposed design is immune to noise and reliable under different parametric variations.

Power-Oriented Monitoring of Clock Signals in FPGA Systems for Critical Application.

This paper presents a power-oriented monitoring of clock signals that is designed to avoid synchronization failure in computer systems such as FPGAs. The proposed design reduces power consumption and increases the power-oriented checkability in FPGA systems. These advantages are due to improvements in the evaluation and measurement of corresponding energy parameters. Energy parameter orientation has proved to be a good solution for detecting a synchronization failure that blocks logic monitoring circuits. Key advantages lay in the possibility to detect a synchronization failure hidden in safety-related systems by using traditional online testing that is based on logical checkability. Two main types of power-oriented monitoring are considered: detecting a synchronization failure based on the consumption and the dissipation of power, which uses temperature and current consumption sensors, respectively. The experiments are performed on real FPGA systems with the controlled synchronization disconnection and the use of the computer-aided design (CAD) utility to estimate the decreasing values of the energy parameters. The results demonstrate the limited checkability of FPGA systems when using the thermal monitoring of clock signals and success in monitoring by the consumption current.

Clock signal distribution with second order nodes: Design hints

Despite being in use since the 1960’s, clock distribution networks continue to be important, mainly since the digitalization of numerous electronic tasks, which demands precise time measures for synchronizing internal and external processes in computational and instrumentation applications. Designing clock distribution networks requires determination/estimation of the appropriate topologies and parameters that guarantee the mutual synchronization of the coupled oscillators. This problem has been largely studied in the telecommunications context, with digital hierarchies succeeding at providing precise multiplexing and switching, integrating services, and in the process, giving rise to a new era of communication. From a mathematical viewpoint, this work considers linear coupling factors, with the study of nonlinear effects still open. As the nodes of time distribution networks are phase-locked loops, considering nonlinearities is helpful for the design and operation of such systems. Herein, an overview of possible solutions concerning topologies and parameters is presented, allowing performance hints regarding network architectures and parameters to help designers. The main contribution is to put together and compare each solution while taking nonlinearities into account and to associate the application to be supported with the best clock distribution solution, thus providing simple rules of thumb for system design.

Coherent Signal Processing for Loosely Coupled Bistatic Radar

Sensitivity and performance of homodyne radar are notably improved if the phase noise terms of transmit and receive signals are correlated and canceled out by the receiver. However, in a bistatic setup with separate oscillators, this correlation is inherently not given. To achieve a good carrier phase and phase noise coherency, it is required to transmit a radio frequency (RF) reference, e.g., by using high-quality RF cables, optical fibers, or wireless point-to-point links. All these options are complex, costly, and prone to distortions and signal delay variations. Sharing a clock signal is also barely helpful since even small distortions of this reference are converted to notable uncorrelated phase noise in the radar signal synthesizers. In this article, a novel full-duplex system concept and signal processing scheme is presented that solves the above-mentioned problems completely. This concept allows for coherent measurements within a bistatic radar setup, even if the two radar stations are only loosely coupled employing a simple clock-rate adjustment. By theory and experimental results with bistatic frequency-modulated continuous-wave radar, it is shown that our concept allows for bistatic measurements with the same sensitivity and performance that is usually only known from homodyne radar systems. To the authors' best knowledge, this is the first time that phase noise coherent measurements in a bistatic multiple-input multiple-output radar setup are shown. This concept paves the way for advanced netted radar setups, e.g., in automotive radar and applications with large apertures or baselines or multiperspective coherent tomographic measurements.

A 12‐Gb/s serial link transceiver using dual‐mode pulse amplitude modulation scheme in a 0.18‐μm CMOS process

SummaryA 12‐Gb/s 0.18‐μm complementary metal oxide semiconductor (CMOS) serial link transceiver with embedded clock signal in data stream using dual‐mode pulse amplitude modulation is presented. The 6‐bit data and the clock signal are both transferred through the same transmission channel. In the proposed modulation technique, the clock signal is easily recovered using a conventional phase‐locked loop without any complex encoders in the transmitter circuit. The transmitter includes multiplexers, an output driver, and pre‐emphasis circuitry with 127‐mW power consumption. The receiver is composed of a phase‐locked loop for clock recovery and demodulator blocks for data recovery, and it dissipates 45 mW of power.

Моделирование блока восстановления тактовой частоты и данных на основе схемы фазовой автоподстройки частоты

In many VLSIs, full amplitude CMOS drivers are used for information transfer via unterminated line. What is more, path length decreases carrying capacity of such interconnection in a greater degree than CMOS drivers’ performance. Because transmit channel considerably garbles transferred information, prevailing solution to this problem are clock data recovery blocks the role of which is to retrieve data along with recovering clock signal. In this work, the process of constructing a clock signal and data recovery unit based on a single-loop phase-locked-frequency scheme that does not require a reference periodic signal is considered. The development of its behavioral model was carried out in the Verilog-AMS hardware description language, and the block modeling at the transistor level was carried out in the 90 nm CMOS technology. In this case, the recovery time was 4.8 microseconds, and the «jitter» indicator of clock signal recovery unit was 7.6 ps. The obtained values of developed clock signal and data recovery unit’s output parameters are up to the best foreign analogues.

Characterization of DAC Phase Offset in IEC 61850-9-2 Calibration Systems

This article presents an accurate and robust method to calculate the phase offset of a reference waveform, usually produced by a digital-to-analog converter (DAC) in IEC Std 61850-9-2 calibration systems. The phase offset is defined with respect to the rising edge of a reference clock signal, locked to the Global Positioning System (GPS). The proposed method relies on the synchronous acquisition of the DAC output and the clock signal. In the complex plane, where the discrete Fourier transform (DFT) is defined, the acquired signals are processed to compensate the nonideal sampling rate and windowing. The method performance and its dependence from noise and parameters are thoroughly characterized by means of extensive numerical simulations. Two validation approaches, experimental and software-based, confirm the proposed method as a valuable and robust solution for calibration purposes.

A Physical‐Layer UHF RFID Tag Collision Resolution Based on Miller Code

In an ultrahigh frequency (UHF) radio frequency identification (RFID) system, the throughput can be greatly improved by collision resolution on a physical layer when tags collide, and high‐performance coding technology can improve the bit error rate (BER) performance of the physical‐layer separation. Most of the traditional physical collision resolutions focus on the code with a single subcarrier. This paper pays more attention to Miller code with multiple subcarriers and proposes a novel physical‐layer separation method based on the Miller code. In this method, the separated collision signals are multiplied by clock signals with the same frequency as the subcarrier to complete the frequency shift. And then, a coherent demodulation and a low‐pass filter are used to remove high‐frequency separation noise. In the simulation, the Miller code with more subcarriers has lower BER than FM0 code with a single carrier. Especially when Miller 8 is selected, the separation efficiency and BER performance of the proposed method are 4 dB higher than those of the traditional XOR method at lower SNR.

Trivium Stream Cipher Countermeasures Against Fault Injection Attacks and DFA

Attacks on cryptocircuits are becoming increasingly sophisticated, requiring designers to include more and more countermeasures in the design to protect it against malicious attacks. Fault Injection Attacks and Differential Fault Analysis have proven to be very dangerous as they are able to retrieve the secret information contained in cryptocircuits. In this sense, Trivium cipher has been shown to be vulnerable to this type of attack. This paper presents four different fault detection schemes to protect Trivium stream cipher implementations against fault injection attacks and differential fault analysis. These countermeasures are based on the introduction of hardware redundancy and signature analysis to detect fault injections during encryption or decryption operations. This prevents the attacker from having access to the faulty key stream and performing differential fault analysis. In order to verify the correct operation and the effectiveness of the presented schemes, an experimental system of non-invasive active attacks using the clock signal in FPGA has been designed. This system allows to know the fault coverage for both multiple and single faults. In addition, the results of area consumption, frequency degradation, and fault detection latency for FPGA and ASIC implementations are presented. The results show that all proposed countermeasures are able to provide a fault coverage above 79% and one of them reaches a coverage of 99.99%. It has been tested that the number of cycles for fault detection is always lower than the number of cycles needed to apply the differential fault analysis reported in the literature for the Trivium cipher.

2 ps Time-to-Digital Converter for Frequency Synthesis in 55 nm CMOS Technology

This paper presents a 2-ps time-to-digital converter (TDC) in 55 nm CMOS technology for all-digital phased-locked loop (ADPLL) system. Innovative inverter delay chain and Vernier delay chain cascade structure is adopted in the TDC to expand the measurement range while ensuring high resolution, so as to meet the wideband application requirements. Time window technology is employed to reduce circuit working frequency to save power by extracting single rising/falling edge of clock signal. Multiplexing technology is exploited to further reduce the power consumption by reusing the rising/falling edge detection delay chain of the first-level TDC, and also the time deviation detection circuit and resolution scaling factor detection circuit of the second-level TDC. The TDC features a differential nonlinearity (DNL) of 0.31 least significant bits (LSB) and an integral nonlinearity (INL) of 0.62 LSB, with a total current consumption of 4 mA from a 1.2 V supply voltage.

Evaluation of systematic uncertainty for transportable <sup>87</sup>Sr optical lattice clock

Transportable optical clocks have broad applications in scientific research and engineering. Accurate evaluation of systematic uncertainty for the transportable <sup>87</sup>Sr optical lattice clock is a prerequisite for the practical realization of the optical clock. Four main frequency shifts of the <sup>87</sup>Sr optical lattice clock are measured, i.e. blackbody-radiation (BBR) shift, collision shift, lattice alternating current (AC) Stark shift, and second-order Zeeman shift. Firstly, by measuring the temperature distribution on the surface of the magneto-optical trap cavity and analyzing the influence of different heat sources on atomic cloud, the BBR shift correction is measured to be 50.4 × 10<sup>–16</sup> Hz with an uncertainty of 5.1 × 10<sup>–17</sup>. Secondly, the time-interleaved self-comparison method is used under high and low atom density condition to evaluate the collision shift of the system. The correction of collision shift is 4.7 × 10<sup>–16</sup> with an uncertainty of 5.6 × 10<sup>–17</sup>. Thirdly, the lattice AC Stark shift is evaluated by the time-interleaved self-comparison method. By measuring the dependence of the lattice AC Stark shift on the wavelength of the lattice light, the magic wavelength is measured to be 368554393(78) MHz. As a result, the lattice AC Stark shift correction is 3.0 × 10<sup>–16</sup> with an uncertainty of 2.2 × 10<sup>–16</sup>. Finally, using the time-interleaved self-comparison technology, the second-order Zeeman frequency shift is evaluated by measuring the fluctuation of the difference in center frequency between the <inline-formula><tex-math id="M300">\begin{document}${m_{\text{F}}} = + {9 / 2} \to {m_{\text{F}}} = + {9 / 2}$\end{document}</tex-math><alternatives><graphic xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="3-20201204_M300.jpg"/><graphic xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="3-20201204_M300.png"/></alternatives></inline-formula> polarization spectrum and <inline-formula><tex-math id="M301">\begin{document}${m_{\text{F}}} = - {9 / 2} \to {m_{\text{F}}} = - {9 / 2}$\end{document}</tex-math><alternatives><graphic xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="3-20201204_M301.jpg"/><graphic xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="3-20201204_M301.png"/></alternatives></inline-formula> polarization spectrum. The correction of second-order Zeeman shift is calculated to be 0.7 × 10<sup>–16</sup>, and corresponding uncertainty is 0.2 × 10<sup>–17</sup>. Experimental results indicate that the frequency shift correction due to the blackbody radiation is the largest, while the uncertainty caused by the lattice AC Stark effect is the largest in the evaluated shifts. The systematic shift is 58.8 × 10<sup>–16</sup>, the total uncertainty is 2.3 × 10<sup>–16</sup>. In the next work, the magneto-optical trap cavity will be placed in a blackbody-radiation cavity to reduce the blackbody-radiation shift. The uncertainty of the collision shift will be reduced by increasing the beam waist of the lattice and reducing the potential well depth of the lattice, which will reduce the density of atoms. What is more, the light source for the optical lattice after spectral filtering will be measured by an optical frequency comb locked to the hydrogen clock signal to reduce the uncertainty of the lattice AC Stark frequency shift. The systematic uncertainty is expected to be on the order of 10<sup>–17</sup>. The evaluation of the systematic uncertainty for the transportable <sup>87</sup>Sr optical lattice clock lays the foundation for the practical application.

A Method of Low-Cost Pure-Digital GPS Disciplined Clock for Improving Frequency Accuracy and Steering Frequency Through TAF-DPS Frequency Synthesizer

One of the key characteristics of modern devices is time-awareness, which demands frequency source of good accuracy, precision, and stability. Unfortunately, all high-quality sources are expensive and bulky. An alternative is to add a companion clocking circuit to the primary source for performing frequency compensation in real time, under the guidance of a good time or frequency reference. The companion circuit aims at counteracting the primary source's systematic error and environment-induced variations. In this work, a frequency synthesizer having the features of small frequency granularity and fast frequency switching is adopted as such companion circuit. It functions as a tuning tool for periodically adjusting device's output frequency under the supervision of 1 PPS signal locked to global positioning system (GPS). This clock disciplining method can also be used for steering output frequency away from the specified value and toward a user-defined target. The main focus of this method is on improving frequency accuracy. The key advantage of the proposed method is low-cost and high-accessibility. It provides a new perspective, or devises a new instrument, for dealing with the sophisticated task of real-time frequency compensation. Our primary goal is to significantly simplify the engineering effort of this task without sacrificing the quality of clock signal noticeably. An field-programmable gate array (FPGA)-based system is created to demonstrate its capability of frequency compensation and steering. Further, 20 such systems are used to study the precision of a multi-node organization, as an example of using this instrument as a syntonization tool. The handy implementation on FPGA illustrates the advantage of DIY (do it yourself), making this method conveniently applicable for a variety of user scenarios.

An 11.05 mW/Gbps Quad-Channel 1.25-10.3125 Gbps Serial Transceiver With a 2-Tap Adaptive DFE and a 3-Tap Transmit FFE in 40 nm CMOS

This paper presents a quad-channel 1.25-10.3125 Gbps wireline transceiver implemented in 40 nm CMOS technology. The transmitter consists of a bit width adjustment, a 40:2 multiplexer, a 2:1multiplexer, and a current-mode logic driver with a 3-tap feedforward equalizer. The receiver has a two-stage continuous-time linear equalizer, a 2-tap half-rate fully adaptive decision-feedback equalizer, a phase interpolation-based digital clock and data recovery (CDR) followed by a 2:40 demultiplexer, a bit width adaption. The transceiver also supports AC/DC coupling, CDR locking detection, PLL locking detection, loss of signal detection, automatic termination impedance calibration. A ring VCO-based PLL is designed in each lane to save power consumption, and a dual-core LC VCO-based PLL is implemented in each bank to generate a low jitter clock signal. At 10.3125 Gbps, the transceiver can equalize 28 dB Nyquist loss at a bit error rate of 10−12, and it consumes 114 mW with a 1.1 V supply. This work presents a high power efficiency of 11.05 mW/Gbps, and the transceiver is suitable for multi-standard applications due to its flexibility and power efficiency.

Research on Clock Circuit Electromagnetic Emission Test and Suppression

Clock circuit is an important part of PCB, which is usually composed of crystal oscillator, crystal oscillator control chip and capacitor. Electromagnetic emission generated by clock circuit is one of the main interference sources of electronic equipment. According to the different transmission paths, electromagnetic interference caused by clock circuit usually includes conduction interference and radiation interference. When the electromagnetic emission generated by the clock circuit reaches a certain degree, it may affect the electromagnetic compatibility of electronic equipment. In this paper, by analyzing the frequency spectrum characteristics of the clock signal, the difference of the frequency spectrum of the clock signal under different parameters is compared, and the electromagnetic emission test method is given. On this basis, when the EMI suppression method of clock circuit is studied, a series of EMC design methods of clock circuit are summarized, and the application of spread spectrum technology in clock circuit is proposed.

Enhancing network-on-chip performance by 32-bit RISC processor based on power and area efficiency

This papers deals with base design of the RISC-V 32b processor. It is used to support many additional commands including hardware loops, post-upgrade and save instructions and additional ALU instructions. RISC processors can be used in different ways, depending on speed and power consumption. Organized to design low power RISC processors through design and solution processes. The speed can also be increased by using the correct clock method. Decoding of execution, memory and rewriting. A one-sided clock signal is used for the middle stage. MIPS V adds a new data type, Single Associated (PS), which stores two single-point floating point numbers (32-bit) in a list of 64-bit floating point numbers. Existing floating point statement variants have been added for arithmetic operations, suitability and limitations to work with this type of data using the SIMD method. New instructions for downloading, transferring and transferring PS data have been added. This is the first command to skip the floating point SIMD with the available fonts.

Investigation of Homo and Hetero-Junction Double-Gate Tunnel-FET-Based Adiabatic Inverter Circuits

ABSTRACT This paper compares the performance of adiabatic inverter circuits employing homo/hetero-junction-based double-gate tunnel field-effect transistors (DG-TFETs). The static and dynamic adiabatic inverter circuits are constructed and they are operated by a sinusoidal power clock signal. The static adiabatic inverter circuits quasi-static energy recovery logic (QSERL), complimentary energy path recovery logic (CEPAL), glitch-free cascadable adiabatic logic (GFCAL) and dynamic adiabatic inverter circuits, clocked adiabatic logic (CAL), pass-transistor adiabatic logic (PAL), single-phase source coupled adiabatic logic (SCAL) are taken into consideration. The circuit performances are evaluated in terms of their power dissipation and delay. In static adiabatic inverter circuits, the homo/hetero-TFET-based GFCAL circuit shows better performance in terms of power and delay than QSERL and CEPAL. In dynamic adiabatic inverter circuits, the homo/hetero-TFET-based PAL circuit demonstrates better improvement in terms of power and delay than CAL and SCAL.