An Asynchronous Bundled-Data Barrel Shifter Design That Incorporates a Deterministic Completion Detection Technique

Abstract

A design for an asynchronous bundled-data barrel shifter that incorporates a deterministic completion detection circuitry is proposed. A bundled-data asynchronous circuit is inherently free from challenges associated with clock signals, but it is devoid of information pertaining to propagation delay through the circuit. An obvious solution is to produce the acknowledge signal at least <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\delta $ </tex-math></inline-formula> delay units after the arrival of the request signal, where <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\delta $ </tex-math></inline-formula> is the maximum propagation delay through the circuit. However, similar to synchronous circuits, such bundle-data asynchronous approach does not take advantage of times where the propagation delay through the circuit is less than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\delta $ </tex-math></inline-formula> . This brief proposes a design for a deterministic completion detection scheme for an asynchronous bundled-data barrel shifter. Once the request signal is active, the shifting operation begins, and the acknowledge signal is generated after a delay that matches the actual shifting delay associated with the shift amount using a deterministic completion detection scheme. The shifter can reduce the idle time between the time its output is ready and the start of the next shift cycle by using a deterministic completion detection circuit. In this brief, the proposed design of the asynchronous barrel shifter and its average delay is analyzed. Its performance is also compared against its synchronous counterpart.