Clock Recovery Research Articles

A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS

This article presents a 48-Gb/s four-level pulse amplitude modulation (PAM-4) receiver with a Baud-rate clock and data recovery (CDR) suitable for multi-level signaling. By deriving the relation between the vertical eye margin (VEM) and the ratio of main-cursor to pre-cursor, the proposed Baud-rate phase detector (BRPD) adjusts the pre-cursor and finds the lock point with targeted vertical eye opening. Thus, the BRPD offers a unique lock point when used with an adaptive decision feedback equalizer (DFE) where post-cursor <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$h_{1}$</tex-math> </inline-formula> is removed. Otherwise, the lock point could drift with the conventional Mueller–Müller phase detector (PD). Furthermore, a summer loading of the DFE reduces the input loading of the DFE by embracing the RZ sampler output instead of the conventional NRZ output, which adds to the delay associated with an RS latch. A prototype chip fabricated in 40-nm CMOS technology consists of an analog front-end (AFE), a phase rotator (PR), a current digital-to-analog converter (DAC), and synthesizable digital logic (SDL), occupying a total active area of 0.24 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> . The proposed PAM-4 receiver achieves a bit-error rate (BER) of less than 10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-11}$</tex-math> </inline-formula> at 48 Gb/s and offers an energy efficiency of 2.42 pJ/b.

Miniaturized Wirelessly Powered and Controlled Implants for Multisite Stimulation.

This paper presents a miniaturized implant with a diameter of only 14 mm, which houses a novel System on Chip (SoC) enabling two voltage level stimulation of up to 16 implants using a single Tx coil. Each implant can operate at a distance of 80 mm in the air through the inductive resonant link. The SoC consumes only 27 μW static power and enables two channels with stimulation amplitudes of 1.8 V and 3.3 V and timing resolution of 100 μs. The SoC is implemented in the standard 180 nm complementary metal oxide semiconductor (CMOS) technology and has an area of 0.75 mm × 1.6 mm. The SoC comprises an RF rectifier, low drop-out regulator (LDO), error detection block, clock data recovery, finite state machine (FSM), and output stage. Each implant has a PCB-defined passcode, which enables the individual addressability of the implants for synchronized therapies. The implantable device weighs only 80 mg and sizes 20.1 mm3. Tolerance of up to 70° to angular misalignment was measured at a distance of 50 mm. The efficacy of bilateral stimulation was further verified by implanting two devices on two sides of a pig's neck and performing bilateral vagus nerve stimulation (VNS), while monitoring the heart rate.

Synchronization and clock recovery in a ferroelectric liquid crystal spatial light modulator based free-space optical communication link.

Synchronization of the transmitter and receiver is crucial in a free-space optical communication system for the proper transfer and retrieval of user information. In this work, we propose a method for the synchronization and recovery of the clock signal at the receiver from the optical signal modulated by a ferroelectric liquid crystal spatial light modulator (FLCSLM) in the transmitter. We have demonstrated our scheme by building an experimental arrangement that comprises an FLCSLM based computer generated holography assembly for modulating the laser beam in the transmitter and a photodiode cum micro-controller circuit in the receiver to generate the synchronized clock. We present the experimental results to demonstrate the accuracy of the recovered clock and the successful retrieval of the transmitted user information. The scheme can work for amplitude modulated, phase modulated, or complex amplitude modulated information transfer based on the FLCSLM.

28 Gbaud PAM-4 Burst-Mode CDR With Reconfigurable Sampling Scheme

This paper presents a fast-locking 28 Gbaud PAM-4 CDR targeting for burst-mode operation. By implementing an oversampling scheme tailored for the preamble stage signal according to the pattern appearance regulation, the trade-off between the loop bandwidth and the convergence time in the conventional CDR is avoided. In addition, to reduce power consumption in the oversampling mode, a 3-phase sampling scheme equivalent to 3 times-oversampling with a minimal phase shift range of 30 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> is proposed. The PAM-4 burst-mode CDR also includes a conventional Bang-Bang phase locking loop with a bandwidth of 5 MHz. Realized in a 65nm bulk CMOS technology, the CDR chip achieves 28 Gbaud PAM-4 burst-mode clock recovery within 10 ns. With integrating slicers, phase interpolators and output buffers, the total power consumption of the CDR is 154 mW. Compared with the prior arts, to the best of authors’ knowledge, the proposed CDR first achieves on-chip phase-locking with PAM-4 Burst signals, based on the proposed PAM-4 burst-mode signal tailored 3-phase oversampling scheme.

A 12-Gb/s Baud-Rate Clock and Data Recovery With 75% Phase-Detection Probability by Precoding and Integration-Hold-Reset Frontend

This brief describes a 12-Gb/s quarter-rate receiver with a current-integrating baud-rate clock and data recovery (CDR) technique. The proposed CDR receives a pre-encoded non-return-to-zero (NRZ) data stream and integrates with 0.5-UI phase offset to extract the phase information. By sampling three consecutive symbols with multiple thresholds in the proposed phase detector, the CDR achieves a 75% phase-detection probability, which is the highest among baud-rate CDRs and leads to a better tracking bandwidth and jitter tolerance. The 12-Gb/s baud-rate CDR prototype is implemented in a 28 nm CMOS process and consumes 77 mW from a 1.2-V supply.

A Time-Domain Simulation Framework for the Modeling of Jitter in High-Speed Serial Interfaces

We report on the development of a time-domain numerical modeling framework to estimate timing jitter in High-Speed Serial Interfaces (HSSI) including a wide range of effects such as Inter-Symbol Interference (ISI) due to channel dispersion, phase noise of transmitter (TX) and receiver (RX) frequency synthesizers and use of bang-bang phase detector in the Clock and Data Recovery (CDR) loop. Based on the step response of the channel, the numerical model computes the response of the system to a random sequence of bits and provides information in terms of eye diagram, bathtub plot and jitter histogram. Different definitions of jitter are investigated, and for each of them we consider the physical effects that are included, eventually identifying that the most complete definition is based on the time distance between the edges instants defined by the CDR and the crossing points of the sampled signal. We also found that this definition is consistent with the features of the bathtub plot. A channel compliant with the PCIe 4.0 standard is used as test vehicle, including the main equalization strategies. The numerical model is then compared to a simple analytical model for the CDR jitter that can be augmented by including Data-Dependent Jitter (DDJ). An approach to system-level analysis based on proper combination of the above elements is eventually proposed to provide quick although accurate aid to the design of CDRs in HSSIs.

TCLink: A Fully Integrated Open Core for Timing Compensation in FPGA-Based High-Speed Links

The high luminosity expected in the second phase of the upgrades of the Large Hadron Collider (LHC phase-2 upgrades) will pose unprecedented challenges to its four experiments in terms of collisions density – also known as pileup – per beam crossing. Disentangling the vertices of 200 simultaneous collisions every 25 ns requires high granularity in the detectors, as well as extremely precise and stable timing. While short-term timing stability is usually a concern addressed in timing distribution systems, long-term variations due to changing environmental conditions can accumulate through distribution chains and can dominate the overall timing stability of the systems they serve. Timing distribution systems in LHC experiments typically use high-speed links and clock recovery. This paper presents a logic core that can be used to mitigate long-term temperature variations in high-speed links. The Timing Compensated Link (TCLink) is an open-source firmware core fully integrated in Xilinx Ultrascale Field Programmable Gate Arrays (FPGAs). It demonstrates picosecond-level phase precision over timing distribution systems, improving the overall timing stability in physics experiments.

A 6.0–11.0 Gb/s Reference-Less Sub-Baud-Rate Linear CDR With Wide-Range Frequency Acquisition Technique

A reference-less sub-baud-rate linear clock and data recovery with a frequency acquisition is proposed to operate from 6 to 11 Gb/s. The proposed frequency acquisition technique operating at a single differential quarter-rate clock and sharing the same phase detector achieves low power consumption. Fabricated in a 28-nm CMOS technology, the frequency detection (FD) logic and locked detector (LD) consume only 0.62 mW. Furthermore, the proposed sub-baud-rate linear phase detector with dead zone free guarantees the in-band recovered phase noise and needs no accuracy reference voltage threshold for phase locking. The proposed sub-baud-rate CDR consumes 8.66 mW, corresponding to power efficiency of 0.86 pJ/bit at 10 Gb/s.

A 100-Gb/s PAM-4 DSP in 28-nm CMOS for Serdes Receiver

This paper presents a dedicated digital signal process (DSP) for four pulse amplitude modulation (PAM4) SerDes receivers. It is targeted to implement data recovery and adaptive equalization under ultra-high-speed and large channel attenuation with a small area and high power efficiency. The DSP consists of a clock data recovery (CDR), a 16-tap feed forward equalizer (FFE), a 1-tap decision feedback equalizer (DFE), and an automatic adaptation engine. An adaptive least mean square (LMS) algorithm is utilized to make the system more intelligent in calculating tap coefficients of the FFE and DFE. To address the timing limitation associated with traditional digital DFE that cannot handle large amounts of parallel data at a high speed, speculative techniques and a customized 4-to-1 multiplexer (MUX) unit are employed to remove the summation time and reduce the selection time, respectively. A first-order sigma-delta modulator is used to replace the traditional moving average to calculate average voltages, which could prominently save the hardware resources and power consumption. Additionally, the influence of input quantization resolution on the equalization ability is analyzed. Implemented in a 28-nm CMOS, the DSP could compensate for up to 33-dB loss at 100 Gb/s with a power consumption of 7.22 pJ/bit.

A 6‐to‐38Gb/s capture‐range bang‐bang clock and data recovery circuit with deliberate‐current‐mismatch frequency detection and interpolation‐based multiphase clock generation

SummaryThis paper reports a bang‐bang clock and data recovery circuit (BBCDR) with an ultra‐wide capture range. The circuit exhibits automatic frequency capture and phase locking over a wide 6‐to‐38 Gb/s range without using a frequency detector, allowed by a recently proposed deliberate‐current‐mismatch technique. Moreover, we accurately obtain an eight‐phase clock through analog interpolation of quadrature signals over the whole wide frequency range by introducing a tunable capacitor array before an inverter‐based phase interpolator. A 65‐nm prototype of the developed BBCDR occupies an area of 0.07 mm2 and attains a bit error rate of less than 10−12 under a continuously variable input frequency, with a total power consumption of 24.6 mW for a 32‐Gb/s non‐return‐zero input, thus leading to 0.769‐pJ/bit energy efficiency.

A 0.2–7.1-Gb/s Low-Jitter Full-Rate Reference-Less CDR for Communication Signal Analyzers

For the measurement of high-speed communication signals, whether it is to check the signal’s bit error rate with a bit error rate tester or to record the signal’s eye diagram with an equivalent-time oscilloscope, a clock and data recovery (CDR) circuit is required to generate a trigger signal properly aligned to the input data signal. For the system under test where multiple communication protocols coexist, a wide operation frequency range and low jitter CDR circuit can undoubtedly improve the measurement efficiency and reduce the cost. However, obtaining broad frequency coverage and minimal recovery clock jitter simultaneously has always been a challenge in the design of CDR circuits. This paper proposes a CDR circuit combining a multi-band LC-VCO and a configurable frequency divider, which effectively expands the operating frequency range of the CDR while maintaining the low jitter of the recovered clock. A 0.2-7.1-Gb/s CDR circuits with a 1.9-ps RMS jitter of the recovered clock under a 7.1-Gb/s input PRBS signal is implemented in 65 nm CMOS. Compared with other LC-VCO based CDRs, the proposed CDR achieves better energy efficiency and lower jitter performance.

Radiation-tolerant all-digital clock generators for HEP applications

The emergence of high-precision timing systems in High Energy Physics motivates new developments in the domain of clock generation and distribution. Particularly, when considering the challenges arising from adopting advanced deep-submicron CMOS technology nodes, all-digital PLL and clock and data recovery (CDR) architectures constitute a promising option for future high energy physics (HEP) experiments. Both LC oscillator and ring oscillator-based all-digital PLL/CDR blocks for front-end ASICs were studied, designed, manufactured and characterized. Their design, the hardening considerations, as well as the performance obtained with these circuits are presented in this article.

Timing and synchronization of the DUNE neutrino detector

The DUNE neutrino experiment far detector has a fiducial mass of 40 kt. The O(1M) readout channels are distributed over the four 10 kt modules and need to be synchronized with respect to each other to a precision of O(10 ns). The entire system needs to be synchronized with respect to GPS time to O(100 ns). The system needs to be reliable, simple and affordable. Clock and synchronization information are encoded on the same fibre using a protocol based on duty cycle shift keying (DCSK) with 8b10b encoding to ensure DC-balance. The use of DCSK allows the clock to be recovered directly by PLL based clock generators without needing to use a separate clock and data recovery (CDR) device. Small scale tests show a timing jitter at the endpoint of ≈10 ps with respect to the timing master.

A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-Based SerDes Receiver With Hybrid AFE Capable of Supporting Long Reach Channels

A 224-Gb/s pulse amplitude modulation 4-level (PAM4) ADC-based SerDes receiver (RX) is implemented in a 5-nm FinFET process. The RX consists of a low-noise hybrid analog front-end (AFE) that incorporates both inductive peaking and source degeneration, a 64-way time-interleaved ADC, digital equalization consisting of an up to 30 tap feed-forward equalizer (FFE), optional decision-feedback equalizer (DFE), and a clock-data-recovery (CDR) loop utilizing a 14-GHz digitally controlled oscillator (DCO). The RX was characterized for medium-to-long reach channels (20.6-, 27-, 31.4-, and 38-dB insertion loss at Nyquist) with a corresponding pre-forward error correction (FEC) bit error rates of 1.9E-11, 5.2E-10, 1.2E-8, and 6E-7, respectively. The analog power consumption of the RX is 1.41 pJ/b.

Simple Low Cost Open Source UHF RFID Reader

In this paper, we present a simple low-cost SDR RFID UHF reader capable of reading a tag in real time. This reader is designed around a simple asynchronous OOK modulator in transmission and an envelope detector in reception. All tasks specific to the RFID protocol including clock recovery, data recovery and frame detection are handled in software by a Arduino Uno micro-controller. This reader is able to generate any RFID command supported by the protocol and to decode any message backscattered by the tag in real time. The details of hardware and software associated with this reader are released in open source for the community.

Hybrid Timing Error Detector for Baud Rate Multilevel Clock and Data Recovery

Hybrid Timing Error Detector for Baud Rate Multilevel Clock and Data Recovery

Phase Interpolator-Based Clock and Data Recovery With Jitter Optimization

Phase Interpolator-Based Clock and Data Recovery With Jitter Optimization

Design and Development of Low Power Clock and Data Recovery Circuit for Asynchronous Network on Chips

Today, the current buffered router Synchronous Network on Chip architecture consumes significant chip area and power. Therefore, based on biased routing, buffer-less routers have recently been predicted as a possible solution, but they suffer from contiguous port assignments, slow critical paths, and increased latency. Asynchronous Network on Chip architecture emerges as the best option for avoiding glitches and consuming less power. A clock and data recovery circuit is used to recover the clock signal from the router-generated data and reduce power consumption in a Multiprocessor System on Chip. This paper proposes a clock and data recovery circuit design for an asynchronous Network on Chip. The proposed 4x4 Mesh router architecture implemented in this paper can process 64-bit of data samples with a depth of 64. When comparing the proposed architecture with the existing NoC architecture, the proposed architecture has shown a power reduction of 5times. The proposed architecture has consumed a total power of 0.103W.

A 21.3-24.5Gb/s low jitter PLL-based clock and data recovery circuit with cascode-coupled quadrature LC-VCO

A 21.3-24.5Gb/s low jitter PLL-based clock and data recovery circuit with cascode-coupled quadrature LC-VCO

A 1.45-pJ/b 16-Gb/s Edge-Based Sub-Baud-Rate Digital CDR Circuit

A 16-Gb/s edge-based sub-baud-rate digital clock and data recovery (CDR) circuit is presented. By using the proposed edge-based sub-baud-rate technique and a passive high-pass filter, the complementary clocks are used to save the power. To improve the jitter tolerance, the intrinsic delay of the high-pass filter is compensated by using compensation delay cells. The proposed sub-baud-rate CDR circuit is fabricated in 40-nm CMOS technology. Its active area is 0.0376mm2 and the power is 23.2mW for a supply of 1.2V at the data rate of 16 Gb/s. The calculated energy efficiency of this CDR circuit is 1.45 pJ/b.