Clock Recovery Research Articles

Real-time Demonstration of a Digital Interpolator-free Clock Recovery for an FPGA-based PM-QPSK Coherent Optical Receiver

Real-time Demonstration of a Digital Interpolator-free Clock Recovery for an FPGA-based PM-QPSK Coherent Optical Receiver

Anti-Singularity Clock Recovery and Rx/Tx IQ Skew Compensation Scheme

Anti-Singularity Clock Recovery and Rx/Tx IQ Skew Compensation Scheme

Single-photon-based clock analysis and recovery in quantum key distribution

Quantum key distribution is one of the first quantum technologies ready for the market. Current quantum telecommunication systems usually utilize a service channel for synchronizing the transmitter (Alice) and the receiver (Bob). However, the possibility of removing this service channel and exploiting a clock recovery method are intriguing for future implementation, both in fiber and free-space links. In this paper, we investigate criteria to recover the clock in a quantum communication scenario and experimentally demonstrated the possibility of using a quantum-based clock recovery system in a time-bin quantum key distribution protocol. The performance of the clock recovery technique, in terms of quantum bit error rate and secret key rate, is equivalent to using the service channel for clock sharing.

A 0.061-pJ/b/dB 28-Gb/s Gradient-Based Maximum Eye Tracking CDR With 2-Tap DFE Adaptation in 28-nm CMOS

This brief presents a gradient-based maximum eye tracking (GMET) scheme employed in the forwarded-clock receiver, including baud-rate clock and data recovery (CDR) and 2-tap adaptive decision feedback equalization (DFE). By optimizing the widely used gradient ascent method for robust operation, GMET achieves low computational power and high stability. Also, simultaneous adaptation using the unified algorithm enables low power consumption and low design complexity. Compared with the previous baud-rate CDR, superior performance is demonstrated under high-loss conditions. The prototype receiver is fabricated in 28-nm CMOS and occupies an active area of 0.106 mm2. At the data rate of 28 Gb/s, the receiver consumes 47 mW, corresponding to an energy efficiency of 1.68 pJ/b. Furthermore, with a channel loss of 27.7 dB at the Nyquist frequency, joint operation of the CDR and the DFE adaptation offers measured results with a margin of 0.17 unit interval (UI) at a BER lower than 10-12.

A 0.99-pJ/b 10-Gb/s Receiver With Fast Recovery From Sleep Mode Under Voltage Drift

This brief presents a 10 Gb/s receiver for an application processor (AP)-to-timing controller-embedded display (TED) interface that is capable of recovering its operating frequency fast from the sleep mode under the supply voltage drift. A hybrid clock and data recovery (CDR) loop is employed to support the fast entering and exiting of the sleep mode by adding AND gates to the digital loop filter, while offering good jitter performance by utilizing an analog loop filter. Also supply voltage drift cancellation (SVDC) circuit is added to maintain constant current in the presence of supply voltage drift. Thanks to the hybrid CDR and SVDC, even if the supply voltage drift occurs during the sleep mode, the same frequency is recovered fast without frequency re-tracking. A prototype chip fabricated in 28-nm CMOS technology occupies an active area of 0.089mm2 with 0.99-pJ/bit energy efficiency in the active mode. The measured results show that the frequency is recovered within 36 ns even if the worst-case supply voltage drift occurs during the sleep mode.

A 103 fJ/b/dB, 10–26 Gb/s Receiver With a Dual Feedback Nested Loop CDR for Wide Bandwidth Jitter Tolerance Enhancement

A 10–26 Gb/s energy-efficient receiver incorporating a dual-feedback nested loop clock and data recovery circuit (DF-CDR) is proposed. Combining a direct modulation path on voltage-controlled oscillator (VCO) and phase interpolator (PI)-based phase rotator inside a phase locked loop (PLL), it improves high-frequency jitter tolerance by 0.15 UI. An edge-first equalization scheme is proposed to reduce power and hardware overhead of decision feedback equalizers. Meanwhile, it facilitates adaptive equalization of continuous time linear equalizer, and background offset calibration of the receiver frontend. A three-stage latch comparator is adopted to enable high-speed direct feedback equalizer. By applying PRBS-31 test pattern through a 32 dB loss channel, the receiver is error-free and features the best energy efficiency of 103 fJ/b/dB at 26 Gb/s.

Low complexity joint clock recovery and adaptive equalization based on a baud-rate timing phase error detector for short-reach digital coherent transmission.

Digital coherent receivers adopting joint clock recovery and adaptive equalization (JCA) can avoid failures of the adaptive equalizer (AEQ) or clock recovery algorithm (CRA) due to clock asynchrony and chromatic dispersion (CD). But in the previous JCA scheme, the AEQ has a heavy computational load as it has to generate two samples per symbol (SPS) for the subsequent timing phase error detector (TPED) which is the core of the CRA. Furthermore, the previous JCA scheme cannot compensate for receiver skew or accommodate Nyquist signals with small roll-off factors (ROFs). These shortcomings hinder its practical applications in ultrahigh-speed short-reach coherent transmission requiring low power consumption, high spectral efficiency, whilst being sensitive to receiver skew. To solve this problem, we propose a new JCA scheme by integrating a two-section real-valued (RV) AEQ with an all-digital feedback CRA based on a baud-rate TPED versatile for different ROFs. Experiments for 61-GBaud dual-polarization (DP) Nyquist 16QAM signals with an ROF of 0.01 show that, compared with the previous JCA scheme, the proposed scheme can reduce the AEQ computational load by about 70% for 10-km transmission, whilst improving the receiver sensitivity by more than 1.7 dB for a receiver skew of 1.5 ps. As far as we know, the proposed JCA scheme is the most comprehensive and efficient solution for ultrahigh-speed short-reach coherent transmission where CD, receiver skew, clock asynchrony, and Nyquist signals with small ROFs have to be dealt with.

A 2–20 Gbps Clock and Data Recovery Based on Phase Interpolation and Delay Locked Loop

A 2–20 Gbps Clock and Data Recovery Based on Phase Interpolation and Delay Locked Loop

Low-latency wavelength-switched clock-synchronized intra-data center interconnects enabled by hollow core fiber.

Fast (nanoseconds) optical wavelength switching is emerging as a viable solution to scaling the size and capacity of intra-data center interconnection. A key enabling technology for such systems is low-jitter optical clock synchronization, which enables sub-nanosecond clock and data recovery for optically switched frames using low-cost methods such as clock phase caching. We propose and demonstrate real-time low-latency wavelength-switched clock-synchronized intra-data center interconnection at 51.2 GBd using a fast tunable laser (with ns scale switching time) and ultra-stable-latency hollow core fiber (HCF) for optically-switched data center networks. For wavelength-switched systems, we achieve a physical layer latency below 46 ns, consisting of 28 ns transceiver latency and a 18 ns inter-packet gap. Finally, we show that by exploiting the low chromatic dispersion and thermally-stable latency features of HCF, active clock phase tracking can be entirely eliminated.

Asynchronous Sampling-Based Hybrid Equalizer

An equalizer architecture based on asynchronous sampling is described. The circuit implementation is a hybrid feed-forward equalizer (FFE) using three digital postcursor taps realized via level-crossing samplers (LCSs) and inverter-based delays. Utilizing a current mode logic (CML)-based summer stage, an analog main tap and digital postcursor taps are combined into an inductively tuned resistor load. With a 0.67-mV-rms simulated output-referred noise, the FFE has better noise performance than a conventional continuous-time linear equalizer (CTLE) and a slicer/latch-based decision feedback equalizer (DFE) circuit. Moreover, it exhibits very good linearity and group delay performance suitable for an equalizer. Using inverter-based delays enables area efficiency as well as the capability to tune the delay across process voltage and temperature (PVT) variations. Since the FFE is an event-driven combinational logic based on the incoming data, it does not require synchronous sampling coming from a high-speed clock and data recovery (CDR), and it is advantageous for high-speed and multirate operation as its power consumption scales with the data rate. Fabricated in 40-nm CMOS technology, the hybrid FFE achieves energy per bit of 2.7 pJ/bit with a 20-dB Nyquist insertion loss link at the 28.57-Gb/s nonreturn to zero (NRZ) data rate.

A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique

This paper reports a reference-less frequency-detector-less single-loop bang-bang clock and data recovery (BBCDR) circuit featuring wide frequency acquisition. We use a current-starved ring oscillator controlled by a 5-bit resistive digital-to-analog converter to maintain quarter-rate operation, supporting a capture range of 110.4%. By the virtue of a deliberate-current-mismatch charge pump pair, we form the single-sided capture scheme in the frequency detection characteristic, eliminating the power-hungry circuits in the high-speed clock and data paths. Employing a hybrid control circuit, the proposed BBCDR automates frequency acquisition and phase tracking in the overall 32 bands. Prototyped in a 65-nm CMOS, the BBCDR covers a wide data rate from 10.8 to 37.4 Gb/s, achieving an acquisition speed of 4.63 (Gb/s)/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula> s and an energy efficiency of 1.3 pJ/bit.

Real-time validation of downstream 50G/25G and 50G/100G flexible rate PON based on Miller encoding, NRZ, and PAM4 modulation

Experimental demonstration is given of a real-time flexible downstream 50 Gb/s passive optical network (PON) mixed with 25 Gb/s or 100 Gb/s signals. 25 Gb/s transmission is enabled by using 25 Gb/s Miller encoding. For back-to-back a lower sensitivity for 25 Gb/s Miller of ∼2.2dB is found relative to 50 Gb/s non-return-to-zero (NRZ). An extended reach of 40 km and up to ∼5dB optical power budget improvement after worst-case 20 km standard single-mode fiber over 50 Gb/s NRZ was shown for 25 Gb/s Miller. It was also shown that optical network units (ONUs) that have 9 dB additional optical received power because they experience a lower optical loss can receive 100 Gb/s four-level pulse amplitude modulation (PAM4) instead of NRZ in a flexible rate PON, which will double the bit-rate to these ONUs. 50 Gb/s NRZ transmission under mixed modulation (50% NRZ and 50% Miller or 50% PAM4) can operate with very low penalty. A power penalty of &lt;0.4dB was found for 50 Gb/s NRZ after worst-case total dispersion (as specified in ITU-T G.9804) when mixed with 25 Gb/s Miller or 100 Gb/s PAM4. For back-to-back there was a smaller penalty of &lt;0.2dB for 50 Gb/s NRZ under mixed modulation. The 25 Gb/s Miller signal spectrum is similar to 50 Gb/s NRZ and 100 Gb/s PAM4, which enables good performance of the real-time clock and data recovery with an integrated adaptive feed-forward-equalizer based equalizer under mixed signal modulation. The increased optical power budget enabled by the 25 Gb/s Miller encoding effectively improves power margins of the high-speed PON and will enable reliable transmission for ONUs deployed with out-of-spec (higher) loss and/or (larger) fiber reach. The additional margin provided by 25 Gb/s Miller encoding will also enable a safe-mode for ONUs that experience out-of-spec scenarios because of faults in the PON fiber network.

A 10-Gb/s 275-fsec Jitter Cryo-CMOS Charge-Sampling CDR for Quantum Computing Application

This letter presents the first clock and data recovery (CDR) system operating at 4.2 K designed for quantum computing (QC) applications. By considering the benefits and challenges of cryogenic operation, a dedicated analog CDR structure is employed so as to maintain high performance at 300 and 4.2 K. The CDR incorporates a new complementary charge-sampling phase detector (PD) that achieves low power and low jitter. Fabricated in 40-nm CMOS, the proposed CDR operates at 10 Gb/s, achieving a recovered clock jitter of 260 fs and a jitter tolerance of 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\rm UI}_{{\rm PP}}$</tex-math> </inline-formula> at a 5-MHz jitter frequency while consuming 4.7 mW at room temperature (RT). At 4.2 K, the power consumption reduces to 3.1 mW with a recovered clock jitter of 275 fs and a jitter tolerance of 0.85 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\rm UI}_{{\rm PP}}$</tex-math> </inline-formula> at a 5-MHz jitter frequency, demonstrating its functionality for a high-speed cryogenic wireline link.

High-precision clock date recovery for optical wireless communications using orbital-angular-momentum-based mode division multiplexing.

In this Letter, we explore the potential of the application of clock data recovery for the implementation of real-time optical wireless communications (OWCs) employing orbital angular momentum (OAM)-based mode division multiplexing (MDM). We experimentally demonstrate a 3-mode multiplexed optical wireless link with a sum rate of 60 Gbps, in which the time synchronization of different channels is realized by the proposed modified digital feedback clock recovery based on the Gardner algorithm. The experimental results show that high-precision channel synchronization with a low timing error can be achieved, and the bit-error rate of all channels can drop below 7% of the hard-decision forward error correction (HD-FEC) limit of 3.8 × 10-3, which indicates that clock data recovery can potentially provide the implementation of real-time OWCs using OAM-based MDM.

The Real-Time System for Distribution of Clock, Control and Monitoring Commands With Fixed Latency of the LHCb Experiment at CERN

The Large Hadron Collider beauty (LHCb) experiment has gone through a major upgrade for LHC Run 3 at European Organization for Nuclear Research (CERN), scheduled to start in the middle of 2022. The entire readout system of the experiment has been replaced by front-end and back-end electronics that are able to record LHC events at the full LHC bunch crossing rate of 40 MHz. To maintain synchronicity across the full system, clock and control commands are originated from a single readout supervisor (SODIN) and distributed downstream through a passive optical network (PON) infrastructure, reaching all the back-end cards of the readout system, via a two-level hierarchy and using PON splitters. A field programmable gate arrays (FPGA) firmware core, called LHCb-PON and based on the CERN timing, trigger, and control (TTC)-PON, is instantiated on SODIN and all back-end cards and provides the communication protocol while ensuring a stable distribution of control commands within the readout period of 25 ns and a clock signal with fixed and deterministic latency with a precision of a few hundreds of picoseconds. This is achieved by the firmware backbone that provides clock recovery and ensures the transmission of a control word downstream with fixed latency. In addition, the LHCb-PON also provides monitoring functionalities over the upstream link, with less strict timing requirements, connecting multiple back-end cards to the central SODIN. This is achieved by having each back-end card send data upstream through a time-division multiplexing (TDM) scheme. This article describes the implementation, measurements, and results from the usage of the system during the startup of the LHC Run 3.

New Clock Distribution System Based on Clock-Duty-Cycle-Modulation for Distributed Data-Aquisition System

This paper presents a clock distribution system based on a clock-centric modulation technique called clock-duty-cycle-modulation (CDCM) using the IOSERDESE2 primitives of Xilinx field programmable gate array (FPGA). The implemented CDCM techniques, CDCM-10-1.5 and CDCM-10-2.5, transfer 1-bit and 2-bit data per clock cycle by changing the trailing edge positions, respectively. This is the first work to succeed transmitting multi-bits per clock cycle by the CDCM. The developed system consists of the CDCM-based transceiver and the link layer protocol. All the components are implemented using the regular bunk functions in FPGA. The system is independent from a FPGA high-speed serial transceiver and does not require a clock data recovery circuit. In this work, two clock generators were utilized for clock recovery; one is a jitter cleaner IC, CDCE62002 from Texas Instruments, and the other is mixed-mode clock manager (MMCM) in FPGA. The 8-bit incremental data was transmitted by the CDCM modulated clock signal through an optical fiber. The jitters of the clock signals recovered by CDCE62002 were 5.8 and 6.8 ps in standard deviation for CDCM-10-1.5 and CDCM-10-2.5, respectively, when the reference clock frequency was 125 MHz. The averaged phase change of the recovered clock signal during the data transmission was smaller than 10 ps with respect to the clock phase recovered from the signal with the duty cycle of 50%. The obtained bit-error-rate (BER) was smaller than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-13</sup> .

Trigger Timing Interface for the Read-Out Upgrade of the Belle II DAQ

To improve data throughput of the Belle II data acquisition we are upgrading the CPU-based COPPER system with a PCIe40 board carrying Arria 10 FPGA. Since one of the main functionalities of the new system is event building in FPGA, the read-out system must be synchronized with the front-end electronics. This task is performed by the bidirectional trigger timing distribution system. During system commissioning, we prepared several versions of the interface to this system. In the initial version of the interface, we ported the code from Xilinx FPGAs to Arria 10. This revision also introduces monitoring of the status for multiple channels and a ring buffer to distribute trigger information to all channels in parallel. To improve stability under external noise, we implemented a clock-data recovery using an independent on-board oscillator as a reference clock in the next revision of the interface. We are also developing a version utilizing a high-speed serial transceiver to replace CAT-7 RJ45 cables with optical fibers. The system commissioning started in 2021 with a few detectors and will be completed after the long shutdown 1 of SuperKEKB in 2023. In this paper, we present the architectures of the interface to the trigger timing system implemented in the PCIe40 board and the system performance in the experiment.

A 0.8-6Gb/s wireline receiver based on the spectrum-balancing equalizer and semi-digital dual loop CDR

In this work, a high-speed four-channel 0.8-6Gb/s wireline receiver was reported. Based on spectrum-balancing (SB) equalizer and slicer amplitude attenuator, it can be automatically adjusted to the most suitable state, avoiding the underbalanced or over-balance caused by amplitude mismatch. Moreover, a first-order semi-digital dual-loop clock and data recovery circuit (SDDCDR) with a high-speed digital loop filter (DLF) is also integrated to simplify the structure and improve the tracking ability of frequency offset. The prototype was fabricated on a 130nm CMOS process with a core area of 0.38 mm2 for a single lane, consuming 97.3mW power at a 1.2V supply and tracking a 6966ppm frequency offset. In a 3m-cable test environment, the receiver sinusoidal jitter tolerance at high frequency is better than 0.22UI when 6Gb/s.

Time-domain low-complexity clock recovery for non-integer oversampled Nyquist signals with a small roll-off factor.

A clock recovery algorithm (CRA) suitable for non-integer oversampled Nyquist signals with a small roll-off factor (ROF) is appealing to short-reach high-speed inter-datacenter transmission systems which need to cut down the transceiver power consumption and cost by reducing the oversampling factor (OSF) and using cheap low-bandwidth components. However, due to the lack of a suitable timing phase error detector (TPED), CRAs proposed now fail for non-integer OSFs below two and small ROFs close to zero and are not hardware-efficient. To solve these problems, we propose a low-complexity TPED by modifying the time-domain quadratic signal and reselecting the synchronization spectral component. We demonstrate that the proposed TPED, in combination with a piece-wise parabolic (PWP) interpolator, can significantly improve the performance of feedback CRAs for non-integer oversampled Nyquist signals with a small ROF. Numerical simulations and experiments show that, based on the improved CRA, the receiver sensitivity penalty can keep below 0.5 dB when the OSF is reduced from 2 to 1.25 and the ROF is varied from 0.1 to 0.001 for 45 GBaud dual-polarization Nyquist 16QAM signals.

A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS

This article presents a 48-Gb/s four-level pulse amplitude modulation (PAM-4) receiver with a Baud-rate clock and data recovery (CDR) suitable for multi-level signaling. By deriving the relation between the vertical eye margin (VEM) and the ratio of main-cursor to pre-cursor, the proposed Baud-rate phase detector (BRPD) adjusts the pre-cursor and finds the lock point with targeted vertical eye opening. Thus, the BRPD offers a unique lock point when used with an adaptive decision feedback equalizer (DFE) where post-cursor <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$h_{1}$</tex-math> </inline-formula> is removed. Otherwise, the lock point could drift with the conventional Mueller–Müller phase detector (PD). Furthermore, a summer loading of the DFE reduces the input loading of the DFE by embracing the RZ sampler output instead of the conventional NRZ output, which adds to the delay associated with an RS latch. A prototype chip fabricated in 40-nm CMOS technology consists of an analog front-end (AFE), a phase rotator (PR), a current digital-to-analog converter (DAC), and synthesizable digital logic (SDL), occupying a total active area of 0.24 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> . The proposed PAM-4 receiver achieves a bit-error rate (BER) of less than 10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-11}$</tex-math> </inline-formula> at 48 Gb/s and offers an energy efficiency of 2.42 pJ/b.