Nowadays FFT architectures are commonly used in a wide range of applications to process real-valued signals and complex-valued signals. Although complex-valued FFT architecture can process both real-valued signals and complex-valued signals a dedicated real-valued FFT architecture is used when real-valued signals are processed because the real-valued FFT architecture requires lesser area. However, there are certain applications that have to process both real-valued signals and complex-valued signals. Under such circumstances, only complex-valued FFT architecture can be used, and architecture is under-utilized when it processes real-valued signals. Therefore, a novel FFT architecture that can process both signals but effectively utilizes the hardware while processing the real-valued signal is proposed. The proposed architecture is based on pipelined MDC FFT architecture, and it can take two input samples simultaneously in normal order and generate output in normal order. While real-valued signals are processed a significant portion of the hardware is disabled by clock gating hence the power consumption is reduced by around 30%. An efficient memory-based structure for reordering the bit-reversed output of both signals is also proposed and the structure roughly uses 50% of the memory when processing the real-valued signal.