Fully Automated Hardware-Driven Clock-Gating Architecture With Complete Clock Coverage for 4 nm Exynos Mobile SOC

Abstract

Automatic clock gating (ACG) is a clock-gating architecture with near zero waste on dynamic power dissipation on global clock distribution network. ACG models global clock structure as a graph with nodes and arcs representing clock components and their interconnections, respectively. Unlike conventional clock structure, where arcs are nothing more than clock nets, ACG adds control mechanism on the arc so that clock gating decision on each clock component can be automated. In this structure, each clock component can understand activities on its fan-outs and can be configured to cut off its output clock when there is no activity. The framework also allows clock consumers to define a period in time where their clock is guaranteed to be present. Combination of these features results in global clock structure, where unnecessary transition on any clock net is automatically avoided. The overall power benefit from this architecture is measured to be 17%–50%.