Inductance enhancement in global clock distribution networks

Abstract

Current research in high-speed clock distribution network focuses on techniques that require a substantial number of analog circuits such as RF clock and PLL arrays (Gutnik and Chandrakasan, 2000) or the introduction of opto-electronic devices (Mule, et al., 2002). This paper presents an alternate approach to increase the bandwidth of global clock lines by inserting passive spiral inductors in global clock networks. Simulations indicate that spiral inductor insertion can be used to obtain a five-fold increase in bandwidth. This technique can be used to extend the use of electrical clock networks currently employed in Cu-CMOS processes.