Clock And Data Recovery Circuit Research Articles

A 0.2–7.1-Gb/s Low-Jitter Full-Rate Reference-Less CDR for Communication Signal Analyzers

For the measurement of high-speed communication signals, whether it is to check the signal’s bit error rate with a bit error rate tester or to record the signal’s eye diagram with an equivalent-time oscilloscope, a clock and data recovery (CDR) circuit is required to generate a trigger signal properly aligned to the input data signal. For the system under test where multiple communication protocols coexist, a wide operation frequency range and low jitter CDR circuit can undoubtedly improve the measurement efficiency and reduce the cost. However, obtaining broad frequency coverage and minimal recovery clock jitter simultaneously has always been a challenge in the design of CDR circuits. This paper proposes a CDR circuit combining a multi-band LC-VCO and a configurable frequency divider, which effectively expands the operating frequency range of the CDR while maintaining the low jitter of the recovered clock. A 0.2-7.1-Gb/s CDR circuits with a 1.9-ps RMS jitter of the recovered clock under a 7.1-Gb/s input PRBS signal is implemented in 65 nm CMOS. Compared with other LC-VCO based CDRs, the proposed CDR achieves better energy efficiency and lower jitter performance.

A 1.45-pJ/b 16-Gb/s Edge-Based Sub-Baud-Rate Digital CDR Circuit

A 16-Gb/s edge-based sub-baud-rate digital clock and data recovery (CDR) circuit is presented. By using the proposed edge-based sub-baud-rate technique and a passive high-pass filter, the complementary clocks are used to save the power. To improve the jitter tolerance, the intrinsic delay of the high-pass filter is compensated by using compensation delay cells. The proposed sub-baud-rate CDR circuit is fabricated in 40-nm CMOS technology. Its active area is 0.0376mm2 and the power is 23.2mW for a supply of 1.2V at the data rate of 16 Gb/s. The calculated energy efficiency of this CDR circuit is 1.45 pJ/b.

A 9.8–12.5 Gb/s Low-Jitter Reference-Less Clock and Data Recovery Circuit

In this paper, we propose a low-jitter reference-less clock and data recovery (CDR) circuit with a speed range of 9.8–12.5[Formula: see text]Gb/s. The proposed CDR uses a multi-stage half-rate bang-bang phase detector (ML-HR-BBPD) to maximize the quantization of the phase difference. In addition, a unit interval adjuster (UIA) is added to the CDR circuit. So that the circuit can minimize the phase detector’s phase error before the output clock frequency is locked. Finally, the loop filter (LF) is improved to realize the coarse and fine adjustment of the phase error over a wide range of phase differences. The CDR circuit’s total power consumption is reduced by using a half-rate phase detector. The CDR circuit was fabricated in TSMC 40[Formula: see text]nm CMOS process. The measured results are obtained in the proposed CDR circuit at a data rate of 12.5[Formula: see text]Gb/s. With a pseudo-random bit sequence (PRBS) of [Formula: see text], the measured result shows that the bit error rate (BER) is [Formula: see text], and the root mean square jitter recovered in the output is 0.302 [Formula: see text]. The circuit’s jitter tolerance (JTOL) is 0.46 UIpp, and its total power consumption is 74.8[Formula: see text]mW with a 5.98[Formula: see text]pJ/bit energy efficiency.

An 18.24-Gb/s, 0.93-pJ/bit Receiver With an Input-Level-Sensing CDR Using Clock-Embedded C-PHY Signaling Over Trio Wires

This article presents a receiver (RX) with an input-level-sensing clock and data recovery (CDR) circuit for a C-PHY interface with trio wires. The proposed CDR circuit detects a “strong” signal from the clock-embedded three-phase-coded signals and recovers the 3-bit wire state and clock simultaneously based on the detected “strong” signal without the inherent switching jitter of conventional C-PHY RXs. Also, the proposed input-level-sensing circuit allows for low power consumption and small size by detecting a “strong” signal without reference voltage or static current consumption, and it automatically compensates for the gain of the analog front end to remain just high enough to detect a “strong” signal even with process, voltage, and temperature variation. This work is implemented using a 28-nm CMOS process with a 1-V supply and occupies an area of 0.022 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , achieving a total energy efficiency of 0.93 pJ/bit at 18.24 Gb/s.

Design Techniques for a 6.4–32-Gb/s 0.96-pJ/b Continuous-Rate CDR With Stochastic Frequency–Phase Detector

This article presents design techniques for a continuous-rate reference-free clock and data recovery (CDR) circuit employing a stochastic frequency–phase detector (SFPD). By taking a histogram-based design methodology, optimal weights for both frequency and phase detection are obtained by utilizing the same information as the Alexander phase detector. The design methodology is inductive and stochastic, distinguished from the conventional, deductive, and procedural methods. To verify a robust operation, the effects of varied data patterns, noise, and channel loss are examined, together with the avoidance of harmonic locking. In addition, a consideration of a sample window is analyzed by fast Fourier transform (FFT) simulation. Fabricated in 40-nm low-power (LP) CMOS technology, the proposed CDR circuit achieves a capture range from 6.4 to 32 Gb/s and a lock time of less than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$11 \mu \text{s}$ </tex-math></inline-formula> . The measured frequency acquisition behavior shows that harmonic locking is avoided with a seamless transition to the fundamental mode. The CDR circuit tested over a 10-dB loss channel achieves a bit error rate (BER) less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−12</sup> and energy efficiency of 0.96 pJ/b.

A Wide-Range FD for Referenceless Baud-Rate CDR Circuits

A wide-range frequency detector (FD) is presented for baud-rate clock and data recovery (CDR) circuits. It achieves a wide frequency capture range, a short lock time, and a low power. By using this FD, a referenceless quarter-rate CDR circuit with a one-tap decision feedback equalizer is fabricated in 40-nm CMOS technology. The active area of this CDR circuit is 0.0999mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and its power is 44mW while the data rate is 16.8Gbps. The calculated energy efficiency of this CDR circuit is 2.62pJ/b.

A 10.4–16-Gb/s Reference-Less Baud-Rate Digital CDR With One-Tap DFE Using a Wide-Range FD

A 10.4-16-Gb/s reference-less and baud-rate clock and data recovery (CDR) circuit with a one-tap speculative decision feedback equalizer (DFE) is presented. The quarter-rate CDR circuit uses a pattern-based phase detector (PD) and the proposed FD. This wide-range FD is composed of a coarse FD and a fine FD (FFD) which share the same front-end comparators with the PD and the DFE. Thus, no extra comparators are required. In addition, by monitoring the drift direction of five samples on the five-bit data patterns, the FFD performs an error-free operation within a frequency error of 7.7%. Therefore, the CDR has a robust FD-to-PD transition. By using the proposed FD, this CDR circuit not only achieves a wide frequency capture range of 43%, but also has a short frequency settling time of $680~\mu \text{s}$ . This CDR circuit is fabricated in 40-nm CMOS technology and occupies an active area of 0.1004 mm2. The total power of the receiver is 39.9mW at 16 Gb/s, and the calculated energy efficiency is 2.49pJ/b.

A 0.32–2.7 Gb/s Reference-Less Continuous-Rate Clock and Data Recovery Circuit With Unrestricted and Fast Frequency Acquisition

This brief presents a design of fast frequency locking 320 Mb/s to 2.7 Gb/s continuous-rate reference-less clock and data recovery (CDR) circuit. A simultaneous coarse/fine frequency acquisition processes are being done to achieve an unrestricted frequency acquisition range and a fast frequency acquisition time. The CDR is implemented in a 180 nm CMOS process, consumes 62 mW of power including I/O buffers at 2.7 Gb/s with a 1.8 V supply. The CDR takes 15.2 μs of a maximum locking time when the data rate locked at 2.7 Gb/s is switched to 320 Mb/s. The CDR circuit has shown 59 ps and 75.4 ps peak-to-peak jitter in recovered clock and data, respectively, with 2.7 Gb/s input data.

A Jitter-Tolerance-Enhanced Digital CDR Circuit Using Background Loop Gain Controller

To improve the jitter tolerance (JTOL) of a clock and data recovery (CDR) circuit, a background loop gain controller (BLGC) is presented. This CDR circuit is realized in a 40nm CMOS process. Its active area is 0.0324mm2 and the power consumption is 12.67mW from a 1 V supply. For 1-Gb/s and 3-Gb/s PRBS of $2^{15}$ -1 and the bit error rate $ , the measured root-mean-square jitter of the retimed data are 12.3ps and 7.74ps, respectively. By using the proposed BLGC, the minimum high-frequency JTOL at 3-Gb/s is improved to 0.68 UIpp.

A 4–20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS

A continuous-rate referenceless clock and data recovery (CDR) circuit with an unlimited frequency acquisition capability is presented. The proposed frequency detector (FD) is derived from a multi-phase oversampling FD. Through accurate analysis of the root causes limiting the capture range, the extension techniques are proposed and digitally implemented by a small hardware overhead. The FD achieves the unlimited frequency detection capability and exhibits robust operation regardless of the initial clock frequency. The effect of the quadrature error is analyzed and verified by simulation. In addition, a frequency lock detector is implemented to control the loop gain for fast frequency acquisition. The prototype CDR circuit was designed and fabricated in a 65-nm CMOS process, occupying an active area of 0.045 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The CDR circuit achieves a capture range from 4 Gb/s to 20 Gb/s, which is limited only by the oscillator operating range. The worst case acquisition time is 25 μs with a PRBS31 pattern. The CDR circuit achieves a BER less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> and an energy efficiency of 1.87 pJ/b.

A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Self-Biased PLL-Based Multiphase Clock Generator

This article presents a four-level pulse-amplitude modulation (PAM4) quarter-rate clock and data recovery circuit (CDR). A quarter-rate linear phase detector (QLPD) is proposed to reduce the recovered clock jitter by removing the dithering jitter of the bang-bang PD. A self-biased phase-locked loop (PLL)-based multiphase clock generator (MCG) with a very wide loop bandwidth (around 600 MHz) is proposed to reduce the MCG power consumption and generate a low-jitter multiphase clock for the quarter-rate operation. Fabricated in a 40-nm CMOS process, the prototype achieves a bit efficiency of 0.46 pJ/bit at 32-Gb/s input data rate. The measured jitter tolerance (JTOL) at the bit error rate (BER) of < 10−12 is higher than 0.35 UIPP with the corner frequency at about 10 MHz. The measured integrated jitter of the 4-GHz recovered clock is 352.6 fs.

A 36-Gb/s Adaptive Baud-Rate CDR With CTLE and 1-Tap DFE in 28-nm CMOS

This letter presents the design details of a 36-Gb/s adaptive baud-rate clock and data recovery circuit (CDR) with continuous-time linear equalizers and 1-tap decision feedback equalizer (DFE) fabricated in 28-nm CMOS. The proposed on-chip adaptation engine is tailored to a baud-rate CDR, where the front-end comparators are shared between the DFE and the PD to save power. The adaptive scheme is demonstrated on a baud-rate CDR testchip that has sampler-based front-end equalization which is more suitable for low-power, short reach, applications instead of a power intensive ADC/DSP-based receiver approach that is usually meant for long-reach (LR) links. This testchip was validated with 34–36 Gb/s random input data (PRBS31 & 7) with channel loss of 15.05–18.25 dB at Nyquist. The total power consumption is measured to be 106.3 mW, equivalent to an FOM of 3.04 pJ/bit at 35 Gb/s.

A 2.41-pJ/bit 5.4-Gb/s Dual-Loop Reference-Less CDR With Fully Digital Quarter-Rate Linear Phase Detector for Embedded DisplayPort

This paper describes a low-power reference-less 5.4-Gb/s clock and data recovery (CDR) circuit with a fully digital quarter-rate linear phase detector (QLPD) having an extended pulse width output. By using a fully digital circuit and merging XOR function with charge pump, the power efficiency and linearity of the phase detector are improved. The proposed QLPD responds correctly up to 0.75 UI of phase difference at 5.4 Gb/s. The CDR was designed to conform to Embedded DisplayPort (eDP) standard of the Video Electronics Standards Association (VESA). The proposed CDR circuit has been fabricated using a 40-nm CMOS technology. The jitter tolerance (JTOL) margin was measured at 0.75 UI, which is 20% higher than the eDP specification of 0.624 UI at the 20-MHz jitter frequency. BER was measured as less than 10−12 with a 27−1 pseudo random bit sequence (PRBS) pattern. The CDR consumes 12.99 mW, including a bandgap reference circuit and power efficiency achieving 2.41 pJ/bit at 5.4 Gb/s. The area of the proposed CDR is 0.13 mm2.

A 0.42–3.45 Gb/s Referenceless Clock and Data Recovery Circuit With Counter-Based Unrestricted Frequency Acquisition

A 0.42 to 3.45 Gb/s counter-based referenceless clock and data recovery (CDR) circuit that has an unrestricted and continuous-rate frequency acquisition capability is presented. The proposed frequency detector first selects a frequency driving direction of the recovered clock using counters and the frequency locking is achieved with the frequency driving direction plus phase information. After that, phase locking is done with the phase-locked loop. The CDR circuit occupied an area of 0.442 mm2 using 180-nm CMOS process. Locking time less than $17.9~\mu \text{s}$ has been achieved from initially the highest data rate of 3.45 Gb/s to the lowest 0.42 Gb/s rate, and vice versa. The CDR circuit has shown 4.33-ps rms jitter in recovered data for a 3.45 Gb/s PRBS31 pattern. The power consumption is 20.3 mW including I/O buffer at 3.45 Gb/s with a 1.8-V supply.

A 32-Gb/s PAM-4 Quarter-Rate Clock and Data Recovery Circuit With an Input Slew-Rate Tolerant Selective Transition Detector

We present a 32-Gb/s PAM-4 quarter-rate clock and data recovery (CDR) circuit having a newly proposed selective transition detector (STD). The STD allows phase detection of PAM-4 data in a simple manner by eliminating middle transition and majority voting with simple logic gates. In addition, using the edge-rotating technique with quarter-rate CDR operation, our CDR achieves power consumption and chip area reduction. A prototype 32-Gb/s quarter-rate PAM-4 CDR circuit is realized with 28-nm CMOS technology. The CDR circuit consumes 32 mW with 1.2-V supply and the recovered clock signal has 0.0136-UI rms jitter.

Optoelectronic Module with Integrated Transceiver and Mux-Demux for Optical Interconnect Applications

The design, development and improvtableement in electronic devices and components have led to the further miniaturization of the system devices and their interconnecting interfaces. Hence, reducing the size of the transmitter (Tx) chips, receiver (Rx) chips and associated components play an important role in designing a reduced/small sized optoelectronic modules for optical interconnect applications. Some of the associated components include multiplexer, demultiplexer, clock and data recovery circuits (CDR), etc. Therefore, in this paper we present an optoelectronic module with integrated transceiver (Tx-Rx) and multiplexer-demultiplexer (mux-demux) with the aim of reducing the total area occupied by the chips. The topology is based on sharing common blocks between Tx and Rx as well as Mux and Demux for saving chip area, power consumption and board area. Based on this topology, a design of 2-channel Tx/Mux and Rx/Demux is realized in a 0.18 μm CMOS technology. The measurement results show clear output eye diagrams at 2.5 Gbps with the voltage swing of 375 mV_pp from the Rx/Demux. The combined solution would save the chip area and power consumption of 10% and 23%, respectively, compared to discrete circuits implementations. Using this topology, a high efficient bidirectional optical link could be implemented in modern computer and other green IT applications.

Up-Conversion of Clock Phase Noise in Plesiochronous Data Links

A great number of recent standards for high-speed data-links permit a small difference, usually measured in parts-per-millions, between transmitter and receiver clock frequencies. Technically known as plesiochronous systems, this small difference in frequency forces the receiver clock and data recovery circuit (CDR) to continuously “rotate” the phase interpolator code to maintain the recovered clock edges always aligned with the incoming data. However, the “rotation” of the phase interpolator causes the phase noise, deterministic and random, of the receiver local clock to be up-converted in frequency. As a result, phase noise components that are normally assumed to be filtered out by the CDR can, in reality, reappear through their up-converted images well above the CDR bandwidth and thus significantly degrades the recovered clock jitter performance. After an intuitive description, this brief provides a mathematical model of the phenomenon and shows how the effect is different based on whether the up-converted phase noise is correlated or un-correlated among the several local clock phases that are used to reconstruct the recovered clock. A standard 10 Gb/s serial link with frequency offset between transmitter and receiver is, then, used as a practical example to describe this phenomenon. The total additional jitter that must be expected at the recovered clock is reported as a function of the frequency offset.

Multilevel Half-Rate Phase Detector for Clock and Data Recovery Circuits

In this brief, a half-rate (HR) bang-bang (BB) phase detector (PD) with multiple decision levels is proposed for clock and data recovery (CDR) circuits. The combination allows the oscillator to run at half the input data rate while providing information about the sign and magnitude of the phase shift between the PD inputs. This allows a finer control of the frequency of the oscillator in the phase-locked loop (PLL) of the CDR circuit, which results in up to 30% less output clock jitter than with a conventional two-levels HR BB PD. Thanks to this, the bit error rate can be decreased by up to $5\times $ in a 5-Gb/s CDR circuit. The proposed topology was implemented in a 28-nm FDSOI CMOS technology providing average power consumption below $76~\mu \text{W}$ with a supply voltage of 1 V. Although multilevel (ML) BB PDs have already been proposed in some PLL-based CDR with very interesting results, a specific design of the PD has to be implemented for an HR system. This brief provides the first ML-HR-BBPD.

3.8 mW 10 Gbit/s CDR for intra‐panel interface with a modulated training pattern

A modulated training pattern for intra-panel interface is proposed and is applied to design power-efficient clock and data recovery (CDR) circuits for intra-panel interface. By modulating the position of the rising edge of the training pattern, the number of the delay cells to generate the multi-phase clock to capture display data safely is reduced. As a result, power, area, and electro-magnetic interference characteristics can be improved over the conventional training pattern. A phase-locked loop-based CDR circuit with the proposed scheme in a 65 nm CMOS technology is designed. The measured lock range was between 6 and 10 Gbit/s and the power efficiency was 0.38 mW/Gbit/s at 10 Gbit/s inputs.

Wide-range tracking technique for process-variation-robust clock and data recovery applications

A wide-range tracking technique for clock and data recovery (CDR) circuit is presented. Compared to the traditional technique, a digital CDR controller with calibration is adopted to extend the tracking range. Because of the use of digital circuits in the design, CDR is not sensitive to process and power supply variations. To verify the technique, the whole CDR circuit is implemented using 65-nm CMOS technology. Measurements show that the tracking range of CDR is greater than ±6×10−3 at 5 Gb/s. The receiver has good jitter tolerance performance and achieves a bit error rate of <10–12. The re-timed and re-multiplexed serial data has a root-mean-square jitter of 6.7 ps.